HYB18RL25632AC Datasheet, PDF (16/37 Pages) Infineon Technologies AG – 256 Mbit DDR Reduced Latency DRAM

HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
2.2 Initialization
The RLDRAM must be powered up and initialized in a predefined manner. Operational procedures other
than those specified may result in undefined operation or permanent damage to the device.
The following sequence is used for Power-Up:
1. Apply power (VEXT, VDD, VDDQ, VREF) and start clock as soon as the supply voltages are stable. Apply
VDD and VEXT before or at the same time as VDDQ, apply VDDQ before or at the same time as VREF.
There is no timing relation between VEXT and VDD, the chip starts the power up sequence only when
both voltages are at their nominal level. However, the pad supply must not be applied before the core
supplies. Maintain all pins in NOP conditions.
2. Maintain stable conditions for 200 µs minimum.
3. Issue three Mode Register Set commands - 2 dummies plus 1 valid MRS (Figure 7).
4. After tMRSC issue 8 Auto Refresh commands, one on each bank and separated by 2048 cycles.
5. After tRC the chip is ready for normal operation.
Figure 7 Power Up Sequence
VEXT
VDD
VDDQ
VREF
CK#
CK
Com.
MRS
MRS
MRS
RF
RF
RF
A.C.
Add
min. 200 µs
BA0
BA1
BA7
t_MRSC
min. 2048 6 x 2048
tRC
cycles cycles
MRS:
RF:
A.C.:
MRS command
REFRESH
Any command
Don't Care
Version 1.60
Page 15
Infineon Technologies
This specification is preliminary and subject to change without notice