HYB18RL25632AC Datasheet, PDF (21/37 Pages) Infineon Technologies AG – 256 Mbit DDR Reduced Latency DRAM

HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
2.5.3 Write Data Mask Timing
2.5.3.3 Burst Length (BL) = 2
Figure 15 Write Data Mask Timing, BL = 2, WL = 2
0
1
2
3
4
5
6
7
8
CK#
CK
Com
WR
WR
WR
WR
WR
WR
WR
WR
WR
Add
A
BA0
A
BA1
A
BA2
A
BA3
A
BA4
A
BA5
A
BA6
A
BA7
A
BA0
DM0
DM1
DQ
WL = 2
D0a D0b
D10bd D2a
D4a D4b D5a D5b D6a
Data not written
into the memory
A/BAx:
WR:
Dxy:
WL:
address A of bank x
W RITE
Data part y to bank x
Write Latency
Don't Care
2.5.3.4 Burst Length (BL) = 4
Figure 16 Write Data Mask Timing, BL=4, WL = 1
0
1
2
3
4
5
6
7
8
CK#
CK
Com
WR
NOP
WR
NOP
WR
NOP
WR
NOP
WR
A
A
A
A
A
Addr
BA0
BA1
BA2
BA3
BA0
DM0
DM1
DQ
WL = 1
D0a D0b D0c D0d
D1c D1d D2a D2b
Data not written
into the memory
A / BAx:
address A of bank x
WR:
Dxy:
WRITE
Data part y to bank x
WL:
Write Latency
Don't Care
Version 1.60
Page 20
Infineon Technologies
This specification is preliminary and subject to change without notice