MB86960 Datasheet, PDF (9/65 Pages) Fujitsu Component Limited. – NETWORK INTERFACE CONTROLLER with ENCODER/DECODER (NICE)

MB86960
SYSTEM CONFIGURATION
A highly integrated system configuration can be achieved
with the NICE controller. Figure 1 illustrates a low chip
count LAN controller with NICE, a bus interface chip
such as Fujitsu’s MB86953 or MB86954, and either a
coaxial transceiver such as Fujitsu’s MBL8392A or a
10BASE-T twisted pair transceiver such as Fujitsu’s
MB86962. Because of its high integration and unique,
innovative architecture, which handles all aspects of
packet management and storage, a local microprocessor
is not required.
The NICE controller connects to the host system bus to
provide command and status interfaces as well as packet
data access. Command and status registers can be directly
accessed by the host processor when mapped into the I/O
or memory space of the host. Through a port on the
device, data packets to be transmitted to the media are
transferred first from host memory to a dedicated buffer
memory for temporary storage until transmitted.
Received data packets are first stored in the buffer
memory, then later transferred to the host memory.
HOST CPU
MAIN
MEMORY
SYSTEM BUS
MB86953 PC
OR MB86954
MCA BUS
INTERFACE
MB86960
NICE
MBL8392A
COAXIAL OR
MB86962
10BASE–T
AUI
TRANSCEIVER
BUFFER
MEMORY
LAN
NETWORK
MEDIUM
Figure 1.Typical System Configuration
Medium Connection
Connection to the LAN medium can be accomplished
with any of the popular connection methods: 1) on-board
connection to unshielded twisted pair through a
10BASE-T transceiver, 2) on-board connection to a thin
50-Ohm coaxial cable through a 10BASE2 transceiver or
3) off-board connection to any other type of medium,
such as standard Ethernet coaxial cable (10BASE5),
through an Attachment Unit Interface (AUI) connector.
NICE has an encoder/decoder (E/D) on chip. An external
encoder/decoder can be used by making the NICE chip
act like a controller alone (depending on customer’s
needs). This option can be changed by using bits 7 and 6
of DLCR7.
Eight pins related to the on-chip E/D can be configured
by DLCR7<7:6> (register DLCR7, bits 7 through 6) to
operate in one of four modes. These pins are TXD, TCK,
TEN, LBC, RXD, RCK, CRS, and COL. In the “Normal
NICE” mode, an internal E/D is used. In this mode, the
pins are all electrically isolated and no signals appear on
the pins. In “NICE + Monitor” mode, all the pins listed
above are outputs whose specific signals appear on the
pins and can be monitored externally. In “Encoder/De-
coder Bypass” mode, an external encoder/decoder is used
with the NICE controller, its own internal E/D is shut
down. In this mode, the pins are either outputs or inputs as
needed to control the external encoder/decoder. In the
“Encoder/Decoder Test” mode, only the E/D on NICE is
active and accessible, the NICE controller section is shut
down. In this mode, the pins are outputs or inputs for an
encoder/decoder, with the opposite control direction of
the outputs or inputs in the “Encoder/Decoder Bypass”
mode. The various possibilities are shown in Figure 2 and
the table below.
DLCR7 DLCR7
Bit 7 Bit 6
Function
0
0 Normal NICE
0
1 NICE plus Monitor
1
0 Encoder/Decoder Bypass
1
1 Encoder/Decoder Test