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| MB86960 Datasheet, PDF (45/65 Pages) Fujitsu Component Limited. – NETWORK INTERFACE CONTROLLER with ENCODER/DECODER (NICE) | |||
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MB86960
SA0-3
CS
RD
RDY
RDY
SD15-0
(from NICE)
t1
TRISTATE
TRISTATE
t3
t5
t4
TRISTATE
t6
t9
t10
t8
Figure 16. Read Cycle
t2
t7
TRISTATE
t11
Table 21. Read Cycle
Symbol
Parameter Description
Min.
Max.
Units
t1
CS low to RD low; SA3â0 valid to RD low
3
ns
t2
RD high to CS high; RD high to SA3â0 invalid
3
ns
t3
RD low pulse width
30
ns
t4
RD low to RDY low
t5
RD low to RDY TRISTATE [1]
0
26
ns
175
ns
t6
RD low to RDY low [2]
0
175
ns
t7
RD high to RDY TRISTATE
28
ns
t8
RD low to SD15â0 valid (except Buffer Memory Port)
44
ns
t9
RDY TRISTATE to SD15â0 valid (buffer port)
8
ns
t10
RDY low to SD15â0 valid
10
ns
t11
RD high to SD15â0 invalid (data hold)
15
ns
1. 0 ns maximum for registers, and for Buffer Memory Port when port is ready before the read cycle begins. For port access only, 175 ns
maximum may occur if system makes contiguous system read cycles at less than 100 ns intervals, and both the transmitter and receiver
are active in âloopbackâ reception. 2.15 µs max for bus read error.
2. 28 ns maximum for all registers. For port access only, 175 ns maximum may occur if system makes contiguous system read cycles at
less than 100 ns intervals, and both the transmitter and receiver are active in âloopbackâ reception. 2.15 µs max for bus read error.
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