MB86960 Datasheet, PDF (18/65 Pages) Fujitsu Component Limited. – NETWORK INTERFACE CONTROLLER with ENCODER/DECODER (NICE)

MB86960
Receive Packet Data Formats
Receive packets, less preamble and CRC fields, are
stored in the buffer along with a four-byte header. The
first byte gives status information, indicating errors, if
any, that occurred during reception of the packet.
Normally packets with errors are automatically
discarded and eliminated from memory by the chip, but
with a mode selection, the chip can allow reception of bad
packets, with indication of their errors in the status byte of
the header. The second byte of the header is reserved for
possible future use. The last two bytes of the header give
the byte count of the packet, less preamble and CRC.
Refer to Figure 9.
SYSTEM INTERFACE
The system interface block provides the connection
between NICE and the host CPU. NICE supports both
8-bit and 16-bit bus widths and byte or word transfers as
determined by DLCR6<5>, SB/SW, the “system byte or
system word” configuration bit. Depending on the type
of host CPU, NICE will supply the data order, MSB or
LSB first according to the setting of DCLR7<0> as
described in the detailed register descriptions. NICE
supports I/O-mapping, memory mapping, and burst or
single transfer DMA modes. An interrupt output, INT, is
provided which may be programmed by the user to
inform the CPU of transmit and receive status conditions
requiring host processing.
Three sets of user-accessible registers are contained
within the MB86960. All registers are accessible as bytes
or words.
Register Access
All control and status registers on the NICE chip are
accessible through its bus interface port, which can be I/O
or memory mapped in the system. Eight of the registers in
the set, whose addresses are xxx0H through xxx7H, are
always directly accessible. For the remaining physical
addresses, three different banks of registers can be
accessed through indirect addressing of the banks (bank
switching). The bank switching bits are part of the first
eight registers which are permanently resident.
The bank-switched register group consists of three sets or
“banks” of registers. One of the sets is for Node ID
(Ethernet Address) and TDR diagnostics, another is the
Hash Table for multicast address filtering, and the third is
for buffer memory access. This third bank is normally
selected most of the time, except during initialization or
diagnostic routines, as access to the other registers is not
needed during normal operation.
Buffer Access
Buffer Memory Port Register 8 (BMPR<8>) of the buffer
memory port register set provides serial access to the
receive and transmit buffers through on-chip FIFO’s.
This port can be accessed with 8-bit or 16-bit wide data.
There is a separate FIFO for each direction of data
transfer, so there is no complicated direction control
needed. Writes to the transmit buffer can be interleaved
with reads from the receive buffer if desired. All buffer
memory pointers are automatically maintained by the
chip, eliminating software overhead normally needed for
this.
This port can be accessed with I/O instructions using
register address xxx8H, or by using DMA. In the latter
case, assertion of the DACK input is sufficient to select
the port. Thus data can be transferred from host memory
to the transmit buffer, or from the receive buffer to host
memory using CPU string moves, single-transfer
programmed I/O moves, or DMA. The choice should be
made according to which is most efficient at a system
level, taking into account that a speedy transfer process
will result in the best performance. A slow transfer
process may not be satisfactory because it might result in
poor throughput and performance, and might allow the
receive buffer to overflow, losing packets.
DMA Operation
The MB86960 supports both single cycle and burst DMA
operation for transfers of data between the host system
and the dedicated buffer memory. The DREQ and DACK
signals are used for handshaking between the external
DMA and NICE. There is also an “end of process” input
pin which, when asserted by the system DMA controller
during a transfer cycle, will terminate the DMA activity
after the current cycle completes. If enabled for DMA
interrupt, upon completion of the DMA activity, the chip
will generate an interrupt.
Usually only one DMA operation will be run at a time,
although the NICE chip could run two interleaving
operations, one reading and one writing. There is only
one DMA EOP bit, and only one DREQ pin and one
DACK pin, so most hosts could not support more than
one DMA operation at a time with NICE.