MB86960 Datasheet, PDF (5/65 Pages) Fujitsu Component Limited. – NETWORK INTERFACE CONTROLLER with ENCODER/DECODER (NICE)

MB86960
PIN DESCRIPTIONS
System Bus Interface Pins (continued)
SYMBOL TYPE
DESCRIPTION
CNTRL
O
CONTROL: This pin is the complement of the register bit CNTRL, DLCR4<2>. It is used to control
external functions.
RMT
O
REMOTE CONTROL PACKET: When DLCR5<2> is set high, this pin follows the RMT 0900H bit
(DCLR1<4>) which indicates that a complete special packet with type field= 0900H has been
received. This is intended for use as a remotely-controlled hardware function from other nodes in
the network.
DREQ
O
DMA REQUEST: Issued to the DMA controller to indicate that NICE has data available to be read in
its receive buffer, of is ready to accept data into its transmit buffer.
DACK
I
DMA ACKNOWLEDGE: Active low, indicate that the DMA controller is ready to transfer data
between the host system and NICE’s buffer memory through BMPR8.
SA<3:0>
I
SYSTEM ADDRESS LINES: Specify which of the internal registers of ports of NICE is selected for
read/write operations.
SD<15:0>
B
SYSTEM DATA BUS: All data, command and status transfers between the host system and NICE
take place over the bidirectional, 3-state, bus. The direction of the transfer is controlled by RD and
WE. The register or buffer port being accessed is selected by a combination of DACK (if active,
selecting the Buffer Port), of the address pins SA3-0 and register bank select bits REG BANK 1 and
REG BANK 0, DLCR7<3:2>. The portion of the data bus over which the transaction occurs is
controlled by SB/SW, BHE, and SA0.
SW/SB
O
SYSTEM WORD/SYSTEM BYTE CONFIGURATION: This signal output reflects the inverse of
DCLR6<5>, SB/SW. If SW/SB=1, the system interface is configured for word transfers, If
SW/SB=0, the system interface is configured for byte-wide transfer on SD7-0, the lower byte.
Note:
B = Bidirectional I/O
I = Standard Input
O = Totem Pole Output
Dual function pins have two
names with the second in
parentheses ( ).