MB86960 Datasheet, PDF (15/65 Pages) Fujitsu Component Limited. – NETWORK INTERFACE CONTROLLER with ENCODER/DECODER (NICE)

MB86960
As shown in Figure 6, the remaining memory not used
for the transmitter is used for the receiver, and is
automatically configured as a “ring buffer” by the chip.
Packets are stored head-to-toe in the receive buffer, as
they are in the transmit buffer. As packets are being stored
in the receive buffer, as the end of the linear addressing
space is reached, the chip’s receive-write pointer
automatically wraps around to the top of the receive
addressing range to make a seamless ring. The
receive-read pointer does the same as the packets are read
out to the system. The MB86960 provides all the
necessary buffer pointer management functions automat-
ically, relieving the host system and its drivers of this
time-consuming task. Since these tasks can be done faster
in hardware than in software, this not only off-loads the
host system, but it also speeds up the communication
processes giving higher throughput.
The buffer controller automatically prioritizes and
services requests for access to the memory from the
transmitter, the receiver, and the host system. It updates all
buffer memory pointers, allocates memory space for
incoming data packets, and controls pertinent bits within
the status registers providing complete packet manage-
ment functions.
HOST CPU
SYSTEM
INTERFACE
READ AND/OR
WRITE
NICE BUFFER
CONTROLLER
TRANSMIT AND
SIMULTANEOUS
RECEIVE
NETWORK
MEDIA
INTERLEAVE
DATA
DEDICATED
BUFFER
MEMORY
Figure 7. Simultaneous Operations and
Buffer Control Capability of NICE
The NICE chip’s arbitration mechanism provides packet
management by interleaving packet data accesses to the
buffer memory so that the operation appears to be
“simultaneous”: data can be written to or read from the
buffer memory by the host via Buffer Memory Port
Register 8 (BMPR8), while data packets are read out for
transmission and/or written in for storage by the receiver.
Each interface, whether host system or network access,
appears to be served independently by the controller.
Each interface has an associated FIFO to provide time for
the buffer interleaving. Thus, packet data is “pipelined”
through the system for highest performance and
throughput, and the buffer controller supports all the
cases of “simultaneous” access to the buffer memory, as
illustrated in Figure 7 and as follows:
1. Data from the network is stored in the receive buffer.
2. The host retrieves packets from the receive buffer.
3. The host loads packet data into the transmit buffer.
4. The transmitter obtains data for transmission from
the transmit buffer.
5. Any combination of the above can occur
concurrently, including all four at once.
System Access to Buffer
NICE supports both programmed I/O, single cycle DMA
and burst mode DMA transfers between the buffer
memory and the host system. The host accesses the buffer
memory by reading from or writing to NICE’s Buffer
Memory Port Register 8 (BMPR8). Data being read or
written by the system passes through on-chip FIFO’s to
eliminate the effects of real-time interaction between the
system, the transmitter and the receiver as they all access
the buffer memory. All read and write operations to the
external SRAM memory are controlled automatically by
the NICE chip.