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MB86960 Datasheet, PDF (47/65 Pages) Fujitsu Component Limited. – NETWORK INTERFACE CONTROLLER with ENCODER/DECODER (NICE)
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MB86960
DREQ
DACK
RD or WE
EOP
RDY
t1
t3
t5
TRISTATE
t2
t4
t6
t7
TRISTATE
RDY
TRISTATE
TRISTATE
Figure 18. Single-Cycle DMA Timing
Table 23. Single-Cycle DMA Timing
Symbol
Parameter Description
t1
DACK low to DREQ low
t2
DACK high to DREQ high
t3
DACK low to RD or WE low
t4
RD or WE high to DACK high
t5
RD or WE low to EOP low
t6
EOP high to DACK high
t7
EOP low pulse width
Min.
0
0
0
3
0
3
10
Max.
21
19
Units
ns
ns
ns
ns
ns
ns
ns
1. An asserted EOP terminates any further DREQ after DACK returns high.
2. The DMA cycle uses DACK as the chip select. DACK overrides CS and SA3-0 if they are both asserted at the same time, forcing
selection of the Buffer Memory Port as in a DMA cycle.
3. For RDY(RDY) timing and SD15-0 timing, see Figure 16, t4-t11, and Figure 17, t4-t9.
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