MB86960 Datasheet, PDF (1/65 Pages) Fujitsu Component Limited. – NETWORK INTERFACE CONTROLLER with ENCODER/DECODER (NICE)

MB86960
NETWORK INTERFACE CONTROLLER
with ENCODER/DECODER (NICE)
DATA SHEET
APRIL1993
FEATURES
• High-performance packet buffer architecture pipe-
lines data for highest throughput
• 20 Mbyte/second data transfer rate to/from the system
bus
• on-chip buffer controller manages pointers, reduces
software overhead
• Efficient, configurable two bank transmit buffer and
ring receive buffer
• Bus-compatible with most popular microprocessors,
including RISC
• Complies with international standards for Ethernet,
ISO/ANSI/IEEE 8802-3
• High-speed burst and single transfer DMA
• 64-element hash table for multicast address filtering
• High-speed, low-power CMOS technology
• Power down mode reduces power dissipation for
battery-powered equipment
• Available in 100-pin plastic quad flat package
two-bank, transmit buffer which allows multiple data
packets to be “chained” together and transmitted to the
network from a single transmit command, thus allowing
greater design flexibility and throughput. Receive
packets are captured in a ring buffer which can be
configured in various sizes from 4 to 62 kilobytes,
depending on memory equipped and amount used for the
transmit buffer.
Possible configurations for the system bus interface
include I/O mapping, memory mapping and DMA
access, or a combination of these. With a 20 Mbyte/sec
bandwidth, the NICE system bus interface allows you to
use the full throughput capacity of its unique packet
buffering architecture. The NICE controller’s selectable
bus modes provide both big- and little-endian byte
ordering, permitting an efficient data interface with most
microprocessors and higher-level protocols.
Implemented in Fujitsu’s high-speed, low-power CMOS
process, the MB86960 is supplied in a 100-pin plastic
quad flat package for surface mounting.
PIN CONFIGURATION
GENERAL DESCRIPTION
The MB86960 Network Interface Controller with
Encoder/Decoder (NICE™) is a high-performance,
highly integrated monolithic device which incorporates
both network controller, complete with buffer manage-
ment, and Manchester encoder/decoder. It allows
implementation of a 7-chip solution for an Ethernet
interface when used with either of Fujitsu’s bus interface
chips, the MB86953 for PC/XT/AT or the MB86954 for
Micro Channel™, and either of Fujitsu’s transceiver
chips, the MBL8392A coaxial transceiver or MB86962
10BASE-T twisted-pair transceiver.
The unique buffer management architecture of the
MB86960 allows packet data to access a buffer memory
area from the host and from the network media
simultaneously, with virtually no interaction. The
network controller updates all receive and transmit
pointers internally, thus reducing the software overhead
required to control these operations, resulting in superior
benchmark speed and application performance. The
NICE device has a partitionable 2, 4, 8, or 16 kilobyte,
100
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81
80
100–PIN
PLASTIC QUAD
FLAT PACK
(PQFP)
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TOP VIEW
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