MB86960 Datasheet, PDF (4/65 Pages) Fujitsu Component Limited. – NETWORK INTERFACE CONTROLLER with ENCODER/DECODER (NICE)

MB86960
PIN DESCRIPTIONS
System Bus Interface Pins
SYMBOL TYPE
DESCRIPTION
RESET
I
HARDWARE RESET: Active high. A minimum pulse of 300 nanoseconds in duration is required.
This pin resets NICE’s internal pointers and registers to the appropriate state.
Note: NICE must be reset after power start before using.
RDY (RDY)
O
READY: This output is asserted to indicate to the host that NICE is ready to complete the requested
read of write operation. It will also be asserted if the device is unable to respond to the request for a
read or write within 2.4 microsecond, In that case, NICE will also assert INT and the bus read error
status bit, DLCR1<6>, or bus write error status bit DLCR<0>. RDY(RDY) may be an active low or
active high signal as determined by RDYPOL, pin 94. If RDYPOL is a “1”, RDY(RDY) will be active
high. If RDYPOL is tied to a “0” RDY(RDY) will be an active low signal.
RDYPOL
I
READY POLARITY SELECT: Control input to select the polarity of RDY(RDY), pin 14. When this
pin is tied high, RDY(RDY) will be active high. If RDYPOL is tied low, RDY(RDY) will be an active
low signal.
WE
I
WRITE: The WE pin is an active low input that enables a write operation form the host system to the
buffer memory port or to internal registers selected by system address inputs SA0-3.
RD
I
READ: Active low input specifies that the current transfer between NICE and the host system is a
read from one of NICE’s internal registers or its data port as selected by SA0-3.
CS
I
CHIP SELECT: This active low input signal is the chip select for NICE.
BHE
I
BYTE HIGH ENABLE: Active Low. This is the byte/word control line. It is used only when NICE is
configured for a 16-bit data bus by the SB/SW bit of DLCR6. It allows word, upper byte only or lower
byte only transfers. The address select pin SA0 is used with BHE for byte or word transfers. as
follows.
SB/SW
0
0
0
0
1
BHE
0
0
1
1
X
SA0 FUNCTION
0
Word transfer
1
Byte transfer on upper half of data bus (SD15-8)
0
Byte transfer on lower half of data bus (SD7-0)
1
Reserved
X
Byte transfer (SD7-0)
INT
O
INTERRUPT: Active low. Indicates that NICE requires host system attention after successful
transmission or reception of a packet, or if any error condition occur, if an EOP (end of process)
signal from the host occurs after the completion of the DMA cycle. The Interrupt signal is maskable
and can be disabled by writing a 0 to the appropriate mask bit.
EOP(EOP)
I
END OF PROCESS: Indicates to NICE that the DMA transfer is finished. When the host DMA
controller asserts EOP(EOP), further assertion of NICE’s bus request output. DREQ, will be
discontinued.
Note:
B = Bidirectional I/O
I = Standard Input
O = Totem Pole Output
Dual function pins have two
names with the second in
parentheses ( ).