MB86960 Datasheet, PDF (24/65 Pages) Fujitsu Component Limited. – NETWORK INTERFACE CONTROLLER with ENCODER/DECODER (NICE)

MB86960
Receive Status Register
This register contains eight status bits which can generate
interrupts if enabled by the corresponding bit in DLCR3.
Five of these bits report the status of the most recently
received packet that was accepted for storage in the
receive buffer. Bit 7, RX PKT, is set whenever a new
packet is successfully received and stored in the buffer.
One bit reports reception of a special packet with 0900H
in its ‘type’ field. Other bits in this register report buffer
overflow, DMA end-of-process and bus read error. Bits 1,
2 and 3 indicate errors, if any, detected in the packet. If
ACPT BAD PKTS, DCLR5<5> and/or ACPT SHORT
PKTS, DLCR5<3> are set to 1 allowing acceptance of a
bad packet, these error bits will be stored in the status
byte of the receive packet header. If DLCR5<5> and
DLCR5<3> are both 0, all packets with detected errors
will be discarded automatically, and removed from
the buffer.
The bits in this register are cleared by writing 1 to the bit.
Writing 0 to the bit has no effect. Only the NICE chip
control logic can set these bits. Clearing the bit that caused
the interrupt will clear both the bit itself and the interrupt.
Since two or more status conditions can occur at one time,
the interrupt routine must read all of them and act on all of
those that are set. See Table 5.
One method for clearing interrupts is to read the contents
of the Transmit and Receive Status Registers, then write
the same value back to the registers, thus clearing all bits
which were set. Another technique is to clear each status
bit separately by writing its mask to the register as the
corresponding interrupt service is performed. Note:
Wholesale clearing of all status bits by writing FFH to the
register is not recommended, since this may clear status
which has just been set and not yet read by the system.
Table 5. DLCR1 — Receive Status Register
BIT SYMBOL TYPE
DESCRIPTION
7
RX PKT
R RECEIVE PACKET: Set when a new receive packet is stored in the Receive Buffer. Can
C generate interrupt if enabled by DLCR3<7>.
0
6
BUS RD
R BUS READ ERROR: Set when a ready response cannot be issued within 2.4 µs after the RD
ERR
C signal is asserted. Occurs when reading an empty buffer. Can generate interrupt if enabled
0 by DLCR3<6>.
5
DMA
R DMA END OF PROCESS: Set when the host DMA asserts the EOP pin indicating that the
EOP
C process is finished. When set, inhibits further assertion of DREQ. Cleared by writing 00H to
0 BMPR12. Do not clear by writing 1 to this bit as this may result in unwanted DREQ. Can
generate interrupt if enabled by DLCR3<5>.
4
RMT
R REMOTE CONTROL PACKET RECEIVED: This bit is set if a packet is received with 0900H
0900H
C in its Length/Type Field (two bytes following the source address, received MSB first). Can
0 generate interrupt if enabled by DLCR3<4>.
3
SHORT
R SHORT PACKET ERROR: Set when a packet is received with less than 60 bytes, excluding
ERR
C its Preamble and CRC fields. Such a packet usually indicates a collision has truncated its
0 original length, since IEEE 802.3 minimum length is 60 bytes. Can generate interrupt if
enabled by DLCR3<3>. See also Table 8.
2
ALIGN
R ALIGNMENT PACKET ERROR: This bit will assert if a packet is received with an alignment
ERR
C error, meaning there were 1 to 7 extra bits at the end of the packet. Such an occurrence
0 usually indicates a collision, or a faulty transceiver. Can generate interrupt if enabled by
DLCR3<2>. See also Table 8.
1
CRC
R CRC PACKET ERROR: This bit is set if a packet is received with a CRC error. This usually
ERR
C indicates a collision has corrupted the packet. Can generate interrupt if enabled by
0 DLCR3<1>. See also Table 8.
0
RX BUF
R RECEIVE BUFFER OVERFLOW: This bit will be set if the receive buffer becomes full and
OVRFLO
C must reject a packet for lack of space. Can generate interrupt if enabled by DLCR3<0>. Does
0 not get set in loopback mode.