MB86960 Datasheet, PDF (20/65 Pages) Fujitsu Component Limited. – NETWORK INTERFACE CONTROLLER with ENCODER/DECODER (NICE)

MB86960
receive DMA process before attempting another DMA
process. This is accomplished by writing 00H to
BMPR12. When this is done, the DMA EOP bit will clear
automatically, clearing the EOP status and interrupt, so
it is not necessary to clear the interrupt separately.
CONTROL AND STATUS REGISTERS
The control and status registers on the NICE chip are
accessed through direct register addresses xxx0H
through xxxFH, and indirect or bank-switching address
bits RBS1, RBS0, DLCR7<3:0>. Table 1 summarizes the
addressing scheme. In system word mode, data can be
transferred 16-bits at a time on the system bus, or 8-bits at
a time by using the byte lane controls of NICE. When
transferring in 16-bit mode to/from the registers, even
direct addresses are used to select the registers. For
example, to access the Transmit/Receive Status Regis-
ters, address xxx0H would be used. The transmit status
would be on the low byte and the receive status on the
high byte. Separate access of high and low bytes is
achieved by using the appropriate byte-access processor
instructions.
Table 1. Internal Register Address Map
RBS1,RBS0 SA3
SA2
SA1
XX
0
0
0
XX
0
0
0
XX
0
0
1
XX
0
0
1
XX
0
1
0
XX
0
1
0
XX
0
1
1
XX
0
1
1
SA0
ADDRESS
DESCRIPTION
0
DLCR0^[1]
1
DLCR1
0
DLCR2
1
DLCR3
0
DLCR4
1
DLCR5
0
DLCR6
1
DLCR7
TRANSMIT STATUS
RECEIVE STATUS
TRANSMIT INT ENABLE
RECEIVE INT ENABLE
TRANSMIT MODE
RECEIVE MODE
CONFIG 0
CONFIG 1
00
1
0
0
0
DLCR8
NODE ID 0
00
1
0
0
1
DLCR9
NODE ID 1
00
1
0
1
0
DLCR10
NODE ID 2
00
1
0
1
1
DLCR11
NODE ID 3
00
1
1
0
0
DLCR12
NODE ID 4
00
1
1
0
1
DLCR13
NODE ID 5
00
1
1
1
0
DLCR14
TDR 0 (LSB)
00
1
1
1
1
DLCR15
TDR 1 (MSB)
01
1
0
0
0
HT8
HASH TABLE 0
01
1
0
0
1
HT9
HASH TABLE 1
01
1
0
1
0
HT10
HASH TABLE 2
01
1
0
1
1
HT11
HASH TABLE 3
01
1
1
0
0
HT12
HASH TABLE 4
01
1
1
0
1
HT13
HASH TABLE 5
01
1
1
1
0
HT14
HASH TABLE 6
01
1
1
1
1
HT15
HASH TABLE 7
10
1
0
0
0
BMPR8^[2]
BUFFER MEMORY PORT
10
1
0
0
1
BMPR9
RESERVED
10
1
0
1
0
BMPR10
TRANSMIT START
10
1
0
1
1
BMPR11
16 COLLISIONS
10
1
1
0
0
BMPR12
DMA ENABLE
10
1
1
0
1
BMPR13
DMA BURST
10
1
1
1
0
BMPR14
SKIP PACKET
10
1
1
1
1
BMPR15
RESERVED
11
X
X
X
X
—
RESERVED
1. All registers are both word and byte accessible. In word mode, register bytes are paired to form words starting with registers 0 and 1. The
odd-addressed byte becomes the high byte of the word
2. In word mode, BMPR8 is a 16-bit port. In byte mode, it is an 8-bit port. The byte ordering Is determined by DLCR7<0>