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MB86960 Datasheet, PDF (16/65 Pages) Fujitsu Component Limited. – NETWORK INTERFACE CONTROLLER with ENCODER/DECODER (NICE)
MB86960
Transmitter Access to Buffer
The size of each of the transmit banks can be changed by
programming the Buffer Size control bits, BS0 and BS1.
The transmit buffer size is thus allocatable by the
software to be a single 2-kilobyte transmit buffer, two
2-kilobyte transmit buffers, two 4-kilobyte transmit
buffers, or two 8 kilobyte transmit buffers. In all
configurations, a single packet or multiple packets can be
loaded into the buffer at one time for transmission. When
a single transmit buffer is used, the system and the
transmitter time-share the use of the buffer. When two
buffers are used, the system can load packets into one of
the buffers while the contents of the other are being
transmitted.
At reset, the pointers are initialized to point to the
beginning of one of the transmit buffers. Each time the
host writes data to the buffer via the Buffer Memory Port
Register, an internal pointer is advanced to the next
memory location within the transmit buffer. Once a data
byte/word is written, it cannot be read and the internal
pointer cannot be reversed.
Internal pointers managed by NICE control which of the
two banks is selected for access by the host and which
byte/word of the bank is accessed. NICE will switch
banks as soon as the transmit start bit (TX START) of
BMPR10 is written high by the host system. When this
occurs, NICE will start transmitting at the earliest
opportunity. Another automatically-managed pointer,
the transmit-read pointer sequences through the bank
being transmitted to read the packet data into the
transmitter through its FIFO. If a collision occurs, the
packet will be automatically retransmitted after a
pseudo-random waiting interval called the backoff
interval. If there are multiple packets in the bank, NICE
will continue down the list, automatically transmitting
them all. The details of this operation are described in the
section on packet transmission.
NICE has the capability to transmit multiple back-to-
back packets of varying legal Ethernet sizes to the LAN
network. These packets may vary in length from 60 bytes
to 1,514 bytes, excluding preamble and CRC fields. As
shown in Figure 8, multiple packets can reside within one
transmit bank, separated by a non-transmitted, two-byte
header which provides the length of the packet in bytes.
Upon reaching the end of the “list” or “chain” of packets,
the transmitter will stop, update it’s status bits and, if
enabled, generate an interrupt.
Transmit Packet Data Formats
The packets to be transmitted, less preamble and CRC
fields, are first loaded into the transmit buffer along with
a two-byte header indicating the packet length in bytes.
See Figure 8 for details. Multiple packets can be loaded at
the same time provided there is room in the buffer. After
the packets are loaded, the host initiates transmission by
writing the number of packets just loaded into a register
for this purpose on the chip. If the two-bank buffer
configuration has been selected, the second bank can
now be loaded with additional packets.
LENGTH LSB
LENGTH MSB
DATA 1
LENGTH LSB
LENGTH MSB
DATA 2
LENGTH LSB
LENGTH MSB
DATA 3
LENGTH LSB
LENGTH MSB
DATA 4
DATA n
UNUSED BUFFER
AREA
PACKET 1
PACKET 2
Figure 8. Transmit Buffer Detail