MB86960 Datasheet, PDF (41/65 Pages) Fujitsu Component Limited. – NETWORK INTERFACE CONTROLLER with ENCODER/DECODER (NICE)

MB86960
Decoder Functions
The data decoder section performs three functions on the
data received at the differential receive inputs (RXDA-
TA±) from the transceiver: clock recovery, carrier
detection and Manchester data decoding.
Clock recovery and data separation are accomplished by
the use of a phase locked loop. Use of proprietary
techniques in the PLL allows lock-on to be accomplished
within 6–7 bit times of the beginning of the preamble,
and permits stable operation with input signal jitter of up
to ±18 ns. Carrier detection is indicated to the controller
by assertion of the CRS signal, which occurs shortly after
a signal appears at RXDATA±.
The recovered clock is supplied to the controller on RCK,
and is also used to convert the Manchester encoded data
to NRZ format. NRZ data is output on RXD. Transitions
in the state of RXD are synchronous with the falling edge
of RCK. During idle periods, RCK is a free-running 10
MHz clock.
The RXDATA± differential inputs are usually terminated
with two 39-Ohm resistors in series and an 0.1mF bypass
capacitor to ground at their junction, as shown in Figure
11.
Monitoring the Network
Whenever the data link section is enabled (DLC EN = 0),
the receiver is constantly monitoring the network for
carrier. Signals which exceed the AC and DC squelch
thresholds of the RXDATA± input section cause the
internal carrier sense (CRS) line to assert, which in turn
causes the receiver to attempt to receive a packet. Refer to
Figure 2 for a block diagram of the encoder/decoder
section. (The carrier sense function is also used by the
transmitter to defer to transmissions from other nodes,
except when DLCR4<0> is high.)
After the PLL decoder acquires bit-synchronization with
the incoming signal, the receiver monitors the data
stream for the end-of-preamble bit pattern, two
consecutive 1’s ending the preamble’s pattern of
alternating 1’s and 0’s. This pattern gives the receiver byte
and field synchronization, because the bit immediately
following the two 1’s is the first bit of the first byte of the
packet’s destination address field.
When packet transmission is unflawed, CRS will remain
asserted for the duration of the packet, negating just after
the last bit has been received. As a packet is coming in, the
decoder’s carrier sense function monitors the data stream
for the end-of-packet symbol, a special non-Manchester
code element at the end of the packet. Upon detecting this
symbol, the carrier sense line will be negated. Loss of
carrier will also result in negation of the carrier sense line,
for example, when a collision occurs.
Receive Packet Processing
As a receive packet comes in from the network, its
destination address field is tested for the various address
filter criteria selected by the Address Filter Mode bits
(AF1, AF0) and the Hash Table. See Figure 15 for
8802–3 packet format. Only if the address meets the filter
criteria selected will the packet be accepted for storage in
the receive buffer. In addition, the packet must be
error-free, unless the chip has been enabled to receive
flawed packets for diagnostic purposes. If these
conditions are met, the packet reception results in the
packet being stored in the buffer, its 4-byte header being
updated at the end of reception, the RX BUF EMPTY bit
being cleared, the RX PKT bit being set high and an
interrupt being generated (if enabled). Otherwise the
packet will be discarded and pointers will be reset to reuse
the same portion of memory for the next packet to arrive.
If a flawed packet is accepted for storage for diagnostic
purposes, its error(s) will be reported in the PKT
STATUS byte of its header (refer to Table 3 for byte and
bit positions).
PREAMBLE
DESTINATION
ADDRESS
Ú₈
6
6
Ú _{END OF}
Ú PREAMBLE
2
BIT PATTERN
SOURCE
ADDRESS
LENGTH/TYPE
Note: (Lengths shown in bytes)
DATA
461500
Figure 15. 8802–3 Packet Format
CRC
Ú₄
ÚÚ _{END OF PACKET}
SYMBOL