MB86960 Datasheet, PDF (27/65 Pages) Fujitsu Component Limited. – NETWORK INTERFACE CONTROLLER with ENCODER/DECODER (NICE)

MB86960
Table 9. DLCR4 — Transmit Mode Register
BIT SYMBOL TYPE
DESCRIPTION
7
COL
R
COLLISION COUNT 3: DLCR4<7:4> plus 1 indicates the number of consecutive collisions
CTR 3
1
encountered by the current transmit packet. (Read only). See Table 10.
6
COL
R
COLLISION COUNT 2: DLCR4<7:4> plus 1 indicates the number of consecutive collisions
CTR 2
1
encountered by the current transmit packet. (Read only). See Table 10.
5
COL
R
COLLISION COUNT 1: DLCR4<7:4> plus 1 indicates the number of consecutive collisions
CTR 1
1
encountered by the current transmit packet. (Read only). See Table 10.
4
COL
R
COLLISION COUNT 0: DLCR4<7:4> plus 1 indicates the number of consecutive collisions
CTR 0
1
encountered by the current transmit packet. (Read only). See Table 10
3
0
N
REVERSED: Write 0.
0
2
CNTRL
R
CONTROL OUTPUT: The inverse of this is bit is output for general use on pin 95.
W
1
1
LBC
R
LOOPBACK CONTROL: This bit controls the loopback function of the NICE
W
encoder/decoder. A 0 in this bit places the chip in internal loopback mode.
1
0
EN TX
R
ENABLE TRANSMIT DEFER: Program this bit low for normal network operation. When
DEFER
W
high, the transmitter will not defer to traffic on the network.
0
Table 10. Collision Count
Collision
Count
16 COL
DLCR0<1>
0
0
1
0
2
0
3
0
.
.
.
.
.
.
15
0
16
1
DLCR4<7>
0
0
0
0
.
.
.
1
0
DLCR4<6>
0
0
0
0
.
.
.
1
0
DLCR4<5>
0
0
1
1
.
.
.
1
0
DLCR4<4>
0
1
0
1
.
.
.
1
0
COL
DLCR0<2>
0
1
1
1
.
.
.
1
1
Receive Mode Register
This register contains six bits which control receiver
function, and one receive buffer status bit. See Table 11.
The status bit, RX BUF EMPTY (Receive Buffer
Empty), is very important to the software routine which
reads receive packets from the buffer. It tells the host
routine whether there are any packets in the receive buffer
which are complete and ready to read. In a multi-tasking
system, this indicator would be used in conjunction with
an interrupt when RX PKT asserts, which means a packet
has arrived in memory. The interrupt would be used to
start the routine which reads packets from the buffer. As
this routine begins, the interrupt on RX PKT can be
disabled to prevent unneeded interrupts. After the first
packet is read from the buffer, the RX BUF EMPTY bit
would be read to see if any more packets have come in
(packets may, at times, arrive in bursts). If the buffer is not
empty, another packet would be read out, and this
procedure repeated until the buffer is empty. After
emptying the buffer, the host clears RX PKT, then
re-enables interrupts on RX PKT, checks the buffer status
one more time (since a packet can come in at any time),
then exits to do other tasks.