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| MB86960 Datasheet, PDF (46/65 Pages) Fujitsu Component Limited. – NETWORK INTERFACE CONTROLLER with ENCODER/DECODER (NICE) | |||
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MB86960
SA0-3
CS
RD
RDY
RDY
SD15-0
(to NICE)
t1
TRISTATE
TRISTATE
t3
t5
t4
t6
TRISTATE
t8
Figure 17. Write Cycle
t2
t7
t9
TRISTATE
Table 22. Write Cycle
Symbol
Parameter Description
Min. Max. Units
t1
CS low to WE low; SA3â0 valid to WE low
3
ns
t2
WE high to CS high; WE high to SA3â0 invalid
3
ns
t3
WE low pulse width
36
ns
t4
WE low to RDY low
0
26
ns
t5
WE low to RDY TRISTATE [1]
t6
WE low to RDY low [2]
175
ns
0
175
ns
t7
WE high to RDY TRISTATE
28
ns
t8
SD15â0 valid to WE high (data setup)
5
ns
t9
WE high to SD15â0 invalid (data hold)
6
ns
1. 0 ns maximum for registers, and for Buffer Memory Port when port is ready before the write cycle begins. For port access only, 175 ns
maximum may occur if system makes contiguous system write cycles at less than 100 ns intervals, and both the transmitter and receiver
are active in âloopbackâ reception.
2. 28 ns maximum for all registers. For port access only, 175 ns maximum may occur if system makes contiguous system write cycles at
less than 100 ns intervals, and both the transmitter and receiver are active in âloopbackâ reception.
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