MB86960 Datasheet, PDF (10/65 Pages) Fujitsu Component Limited. – NETWORK INTERFACE CONTROLLER with ENCODER/DECODER (NICE)

MB86960
CONTROLLER
RXD, RXC
CRS, TCK, COL
TEN, TXD, LBC
ENCODER/
DECODER
NICE
CASE 00: NORMAL NICE MODE
CONTROLLER
ENCODER/
DECODER
NICE
CASE 01: NICE + MONITOR
CONTROLLER TEST
CONTROLLER
ENCODER/
DECODER
NICE
CASE 10: ENCODER/DECODER BYPASS
EED TEST
CONTROLLER
ENCODER/
DECODER
NICE
CASE 01: NICE + MONITOR
Figure 2. Encoder/Decoder Modes
CRYSTAL OSCILLATOR
The ISO/ANSI/IEEE 8802–3 international LAN stan-
dard specifies a bit clock rate of 10 Mbit/sec. This is
obtained from a 20 MHz clock generated by the on-chip
oscillator, which operates from an external crystal
connected between pins X1 and X2 on the NICE chip.
Crystal capacitance as specified by the manufacturer
should be connected from X1 and X2 to ground,
considering any stray capacitance which can vary the
crystal’s frequency. See Figure 3 for typical values. A
crystal with the following specifications is recom-
mended: quartz (AT-cut; 20 MHz; frequency/accuracy of
±50 ppm at 25_C to 70_C; parallel resonant with 20 pF
load in a fundamental mode. Possible vendors include:
Ecliptek Corp. (Costa Mesa, CA), p/n
ECSM200-20.000; and M-tron Industries, Inc. (Yank-
ton, SD), p/n MP-1 & MP-2, with 20MHz, 50ppm over
0_C to 70_C, and 18 pF fundamental load.
NICE
X1
X2
20 MHz
18 pF
18 pF
Figure 3. Crystal Connection
The clock also serves as a reference for an internal phase
locked loop which is used for clock recovery in the
decoder section. Internal clocks are shut down when
DLCR7 bit 5, PWRDN, is invoked for Power Down
Mode.
SRAM CONFIGURATIONS
Eight different configurations of SRAM for the packet
buffer are possible as illustrated in Figure 4. First, the
width of the SRAM data path can be 8 or 16 bits, selected
by programming the Buffer Byte/Buffer Word (BB/BW)
bit, bit 4 of DLCR6. If this bit is set to 1, byte-wide data is
selected; if set to 0, the width is word-wide (16 bits). The
SB/SW Bit, DLCR6 bit 5, selects the system bus width,
while the BB/BW Bit, DLCR6 bit 4 selects the SRAM
buffer width. Secondly, the depth of the SRAM is
programmed by setting Buffer Size 1 and 0 (BS1 and
BS0), bits 1 and 0 in DLCR6. Depth selections are 8, 16,
32 or 64 kilobytes.