MB86960 Datasheet, PDF (48/65 Pages) Fujitsu Component Limited. – NETWORK INTERFACE CONTROLLER with ENCODER/DECODER (NICE)

MB86960
DREQ
DACK
RD or WE
RDY
TRISTATE
RDY
TRISTATE
t₁
t₂
Figure 19. Burst DMA Timing
Table 24. Burst DMA Timing
Symbol
Parameter Description
Min. Max. Units
t₁
RD or WE low to DREQ low
32
ns
t₂
RD or WE high to DACK high
3
ns
1. DREQ goes low during the next-to-last transfer of the burst. DACK should not go high until after the RD or WE pulse of the last transfer
cycle goes high.
2. The DMA cycle uses DACK as the chip select. DACK overrides CS and SA3-0 if they are both asserted at the same time, forcing
selection of the Buffer Memory Port as in a DMA cycle.
3. For RDY(RDY) timing and SD15-0 timing, see Figure 16, t₄-t₁₁, and Figure 17, t₄-t₉.