MB86960 Datasheet, PDF (19/65 Pages) Fujitsu Component Limited. – NETWORK INTERFACE CONTROLLER with ENCODER/DECODER (NICE)

MB86960
DMA Write (Transmit)
Transmit DMA Enable, TX DMA EN, BMPR12<0>, is
set high to enable DMA operation for transfers of data
packets from the host memory to NICE’s transmit buffer.
Burst transfers can also be enabled by invoking the DMA
burst control register BMPR13<1:0>. When NICE is
ready to begin to accept data from the host, NICE will
assert its DMA request output, DREQ. The host responds
by asserting DMA Acknowledge, DACK, followed by
write enable, WE, and placing the data on the data bus.
NICE will assert its RDY(RDY) output when it is ready to
complete the current data transfer cycle (polarity of
RDY(RDY) and EOP(EOP) inputs are independently
programmable). NICE accepts that data byte/word into
its bus write FIFO, and later moves it into buffer
memory. At the close of a transfer cycle, the host negates
WE. In burst mode, NICE will negate DREQ two cycles
before the end of the burst. The host DMA will then
complete the last two transfer cycles, then negate DACK
to close the burst. To start another burst, NICE will
re-assert DREQ. The number of DMA write cycles within
one burst can be 1, 4, 8, or 12 data transfers (bytes or
words) depending on the burst control bits BURST1,
BURST0, BMPR13<1:0>.
The DMA controller may assert the end-of-process
input, EOP(EOP), concurrently with the last data transfer
cycle to indicate that the entire transfer process has been
completed. This sets the DMA EOP bit in NICE which
causes NICE to discontinue making further data requests.
If enabled, the EOP(EOP) signal assertion can also
generate an interrupt. When the DMA EOP bit,
DLCR1<5>, is set, the INT pin will assert if DLCR3<5>,
interrupt enable for DMA EOP , is high. This interrupt
can be used by the host to initiate the actions for closing
the process. Upon servicing the interrupt, if DMA EOP is
high, the host should close the DMA process, reset the
NICE chip’s DMA logic and clear the interrupt by
writing 00H to BMPR12. Note: Clearing TX DMA EN
must be done to close the transmit DMA process before
attempting another DMA process. This is accomplished
by writing 00H to BMPR12. When this is done, the DMA
EOP bit will clear automatically, clearing the EOP status
and interrupt, so it is not necessary to clear the interrupt
separately.
After finishing the loading of packets into the buffer, the
host initiates packet transmission. This is done by
loading the number of packets to be transmitted into the
Transmit Packet Count Register, BMPR10<6:0>, and
asserting the Transmit Start bit, TX START, of the same
register, BMPR10<7>.
DMA Read (Receive)
NICE will indicate when it has receive packets to be read
with status bits and/or interrupts. Before attempting to
read a packet, the host processor first reads the RX BUF
EMPTY bit, DLCR5<6>. If this bit is 0, there are one or
more packets in the receive buffer to read. After reading
each packet, the host will check this bit again to see if
there are more.
Prior to beginning the transfer of a packet from NICE’s
receive buffer to host memory via DMA, the host must
first read the four-byte receive packet header from the
buffer to obtain the packet status and the length of the
packet in bytes. Calculating from the packet length the
number of DMA cycles needed to read the packet, the
host will load that number into the cycle counter of the
host DMA controller. The starting address in system
memory will also be loaded into the DMA controller.
Next, RX DMA EN, BMPR12<1>, is set high to enable
DMA read operation to transfer the packet to host
memory. When it is ready to begin, NICE asserts its DMA
Request output, DREQ. The host responds by asserting
DMA Acknowledge, DACK, followed by Read Enable,
RD. NICE will assert its RDY output when it has placed
the byte/word on the data bus and is ready to complete the
data transfer cycle. The system memory will accept the
data, then the host negates RD. NICE shifts the data down
into its bus read FIFO, then moves its internal bus read
pointer to point to the next byte/word in the buffer,
moving it into the FIFO.
NICE will negate DREQ two cycles before the end of the
burst. After the host negates DACK, if NICE can transfer
more data, NICE will re-assert DREQ to repeat the
process. The number of DMA read cycles in a burst can be
1, 4, 8, or 12 transfer cycles of data (bytes or words),
depending on the burst control bits BURST1, BURST0,
BMPR13<1:0>. The DMA controller may assert the
end-of-process input, EOP(EOP), concurrently with the
last byte/word data transfer to indicate that the entire
process has completed. NICE will then discontinue
making further data requests. RX DMA EN must be
cleared when the DMA process is completed, and set
again when the host desires to begin reading another
packet from the receive buffer using DMA.
When EOP(EOP) is asserted by the host DMA controller,
the DMA EOP bit, DLCR1<5>, will be set high, and an
interrupt will also be generated, provided it is enabled by
a high, DLCR3<5>. This interrupt can be used by the host
to initiate the final actions to close the DMA process. The
interrupt is cleared and the DMA is disabled and reset by
writing 00H to the DMA Enable Register, BMPR12.
Note: Clearing RX DMA EN must be done to close the