MC9S08LC60 Datasheet, PDF (93/358 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 6 Parallel Input/Output
6.2.6.2 Output Slew Rate Control Enable (PTCSE)
Slew rate control can be enabled for each port pin by setting the corresponding bit in the slew rate control
register (PTCSEn). When enabled, slew control limits the rate at which an output can transition in order
to reduce EMC emissions. Slew rate control has no effect on pins which are configured as inputs.
7
R
PTCSE7¹
W
6
PTCSE6²
5
PTCSE5
4
PTCSE4
3
PTCSE3
2
PTCSE2
1
PTCSE1
Reset
1
1
1
1
1
1
1
Figure 6-24. Slew Rate Control Enable for Port C (PTCSE)
1 _{PTCSE7 has no effect on the input-only PTC7 pin.}
2 _{Reads of PTCD6 always return the contents of PTCD6, regardless of the value stored in the bit PTCDD6.}
0
PTCSE0
1
Table 6-14. PTCSE Field Descriptions
Field
Description
7:0
PTCSE[7:0]
Slew Rate Control Enable for Port C Bits — For port C pins that are outputs, these read/write control bits
determine whether the slew rate controlled outputs are enabled. For port C pins that are configured as inputs,
these bits are ignored.
0 Slew rate control disabled.
1 Slew rate control enabled.
6.2.6.3 Output Drive Strength Select (PTCDS)
An output pin can be selected to have high output drive strength by setting the corresponding bit in the
drive strength select register (PTCDSn). When high drive is selected a pin is capable of sourcing and
sinking greater current. Even though every I/O pin can be selected as high drive, the user must ensure that
the total current source and sink limits for the chip are not exceeded. Drive strength selection is intended
to affect the DC behavior of I/O pins. However, the AC behavior is also affected. High drive allows a pin
to drive a greater load with the same switching speed as a low drive enabled pin into a smaller load.
Because of this the EMC emissions may be affected by enabling pins as high drive.
MC9S08LC60 Series Advance Information Data Sheet, Rev. 2
Freescale Semiconductor
PRELIMINARY
93