MC9S08LC60 Datasheet, PDF (342/358 Pages) Freescale Semiconductor, Inc – Microcontrollers

Appendix A Electrical Characteristics
1 _{This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to}
override reset requests from internal sources.
2 _{When any reset is initiated, internal circuitry drives the reset pin low for about 34 cycles of fSelf_reset and then samples the level}
on the reset pin about 38 cycles later to distinguish external reset requests from internal requests.
3 _{This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or}
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
4 _{Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40°C to 85°C.}
RESET PIN
t_extrst
Figure A-12. Reset Timing
BKGD/MS
RESET
t_MSSU
t_MSH
Figure A-13. Active Background Debug Mode Latch Timing
t_ILIH
IRQ
Figure A-14. IRQ Timing
A.10.2 Timer/PWM (TPM) Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that
can be used as the optional external source to the timer counter. These synchronizers operate from the
current bus rate clock.
MC9S08LC60 Series Advance Information Data Sheet, Rev. 2
342
PRELIMINARY
Freescale Semiconductor