MC9S08LC60 Datasheet, PDF (159/358 Pages) Freescale Semiconductor, Inc – Microcontrollers

Liquid Crystal Display Driver (S08LCDV1)
9.5.2.2 Initialization Example 2
Example 2 LCD setup requirements are reiterated in the following table:
Example
2
Operating
Voltage,
V_DD
LCD Clock
Source
LCD Glass
Operating
Voltage
Required
LCD
segments
LCD
Frame
Rate
Blinking
Mode/Rate
Behavior in
STOP3 and
WAIT modes
LCD Power
Input
3.6-V
Internal
3-V
100 kHz
99
80 Hz Individual segment WAIT: on Power via
0.5 Hz
STOP3: off
V_DD
Table 9-23 lists the required setup values required to initialize the LCD as specified by Example 2:
Table 9-23. Initialization Register Values for Example 2
Register
Bit/bit field
LCDCLKS
10000010
LCDSUPPLY
1XXXXX01
SOURCE
DIV16
CLKADJ[5:0]
LCDCPEN
LCDCPMS
HDRVBUF
CPCADJ[1:0]
BBYPASS
VSUPPLY[1:0]
LCDCR1
XXXXXX01
LCDWAI
LCDSTP3
Binary
Value
1
0
000010
1
X
X
XX
X
01
0
1
Comment
Selects the bus clock as the LCD clock input
External clock reference = 0; Bus clock = 1
Adjusts the LCD clock input (see table 9-12)
Adjusts the LCD clock input (see table 9-12)
Enable the charge pump
Don’t care since power is from internal V_DD
Doubler mode = 0; Tripler mode = 1
High drive buffer
Configure LCD charge pump clock source
Buffer Bypass; Buffer mode = 0; Unbuffered mode = 1
Power LCD via V_DD internal power (see table 9-16). When VSUPPLY[1:0] = 01,
V_LL3 is generated from V_{DD .}
LCD is “on” in WAIT mode
LCD is “off” in STOP3 mode
LCDCR0
0X011X11
LCLK[2:0]
LPWAVE
DUTY[1:0]
011 For 1/3 duty cycle, select closest value to the desired 80 Hz LCD frame frequency
(see table 9-13). Note the LCD base frequency - 256.2 Hz
X
Low power waveform
10
For 99 segments (3x33), select 1/3 duty cycle (see table 9-11)
MC9S08LC60 Series Advance Information Data Sheet, Rev. 2
Freescale Semiconductor
PRELIMINARY
159