MC9S08LC60 Datasheet, PDF (130/358 Pages) Freescale Semiconductor, Inc – Microcontrollers

Liquid Crystal Display Driver (S08LCDV1)
9.3.3 LCD Frontplane Enable Registers 0–5 (FPENR0–FPENR5)
When LCDEN = 1, these bits enable the frontplane output waveform on the corresponding frontplane pin.
FPENR0
FPENR1
FPENR2
FPENR3
FPENR4
FPENR5
R
W
Reset
R
W
Reset
R
W
Reset
R
W
Reset
R
W
Reset
R
W
Reset
7
FP7EN
0
FP15EN
0
FP23EN
0
FP31EN
0
FP39EN
0
0
0
6
FP6EN
0
FP14EN
0
FP22EN
0
FP30EN
0
FP38EN
0
0
0
5
FP5EN
0
FP13EN
0
FP21EN
0
FP29EN
0
FP37EN
0
0
0
4
FP4EN
0
FP12EN
0
FP20EN
0
FP28EN
0
FP36EN
0
0
0
3
FP3EN
0
FP11EN
0
FP19EN
0
FP27EN
0
FP35EN
0
0
0
2
FP2EN
0
FP10EN
0
FP18EN
0
FP26EN
0
FP34EN
0
0
0
1
FP1EN
0
FP9EN
0
FP17EN
0
FP25EN
0
FP33EN
0
0
0
0
FP0EN
0
FP8EN
0
FP16EN
0
FP24EN
0
FP32EN
0
FP40EN
0
Read: anytime
Write: anytime
Unimplemented or Reserved
Table 9-6. FPENR0–FPENR5 Field Descriptions
Field
Description
40:0
FP[40:0]EN
Frontplane Output Enable — The FP[40:0]EN bit enables the frontplane driver outputs. If LCDEN = 0, these
bits have no effect on the state of the I/O pins.It is recommended to set FP[40:0]EN bits before LCDEN is set.
0 Frontplane driver output disabled on FPnn.
1 Frontplane driver output enabled on FPnn.
MC9S08LC60 Series Advance Information Data Sheet, Rev. 2
130
PRELIMINARY
Freescale Semiconductor