MC9S08LC60 Datasheet, PDF (84/358 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 6 Parallel Input/Output
6.2.1.1 Port A Data Registers (PTAD)
Port A parallel I/O function is controlled by the data and data direction registers in this section.
R
W
Reset
7
PTAD7
0
6
PTAD6
5
PTAD5
4
PTAD4
3
PTAD3
2
PTAD2
0
0
0
0
0
Figure 6-2. Port A Data Register (PTAD)
1
PTAD1
0
0
PTAD0
0
Table 6-1. PTAD Field Descriptions
Field
Description
7:0
PTAD[7:0]
Port A Data Register Bits — For port A pins that are inputs, reads return the logic level on the pin. For port A
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTAD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.
6.2.1.2 Port A Data Direction Registers (PTADD)
R
W
Reset
7
PTADD7
0
6
PTADD6
5
PTADD5
4
PTADD4
3
PTADD3
2
PTADD2
0
0
0
0
0
Figure 6-5. Data Direction for Port A (PTADD)
1
PTADD1
0
0
PTADD0
0
Table 6-2. PTADD Field Descriptions
Field
Description
7:0
PTADD[7:0]
Data Direction for Port A Bits — These read/write bits control the direction of port A pins and what is read for
PTAD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn.
MC9S08LC60 Series Advance Information Data Sheet, Rev. 2
84
PRELIMINARY
Freescale Semiconductor