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| MC9S08LC60 Datasheet, PDF (153/358 Pages) Freescale Semiconductor, Inc – Microcontrollers | |||
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Liquid Crystal Display Driver (S08LCDV1)
9.4.4.2 LCD Power Supply and Voltage Buffer Conï¬guration
The LCD power supply can be internally derived from VDD or it can be externally derived from a voltage
source in the range between 0.9 to 1.8 Volts that is applied to the VLCD pin. The Table below provides a
more detailed description of the power state of the LCD module which depends on the conï¬guration of the
VSUPPLY[1:0], LCDCPMS, BBYPASS, and LCDCPEN bits.
Table 9-18. VDD Switch Option
LCD Power Supply Conï¬guration
LCD Operational State
0 Initial VLL2 voltage to VDD level.
00 X
X
1
Internal power supply.
VLL2 is generated from VDD.
0 Initial VLL3 voltage to VDD level.
01 X
X
1
Internal power supply.
VLL3 is generated from VDD.
x x 0 Bias voltages not generated.
LCD disabled
LCD operational
LCD disabled
LCD operational
Minimum current consumption
LCD disabled
0
0
1
External power supply for VLCD.
Buffered doubler mode.
LCD operational
Maximum current consumption
10 0
1
1
External power supply for VLCD.
Un-buffered doubler mode.
LCD operational
1
0
1
External power supply for VLCD.
Buffered tripler mode.
LCD operational
1
1
1
External power supply for VLCD.
Un-buffered tripler mode.
LCD operational
Minimum current consumption
11 X
X
0
External power supply for VLL1,VLL2, and VLL3 required.
VLCD pin ï¬oating.
LCD Operational
1 VLCD pin ï¬oating.
Invalid LCD power conï¬guration
Figure 9-18 shows that if VSUPPLY[1:0] = 10 or 11, the LCD module is configured for an external power
source. If VSUPPLY[1:0] = 00 or 01, the LCD power supply is configured to be internally derived from
VDD.
9.4.4.2.1 LCD External Power Supply, VSPUPPLY[1:0] = 10
When VSPUPPLY[1:0] = 10, only the powersw3 signal is asserted and the LCD module is conï¬gured to
be powered via an external voltage input on VLCD (Recall VLCD is speciï¬ed to be in the range from 0.9 V
to 1.8 V). The ï¬gure above shows that VLCD is an input to the voltage divider block and is related to VLL1.
The voltage divider block uses the states of LCDCPMS, BBYPASS, and powersw3 to derive a state for
VLL1.
MC9S08LC60 Series Advance Information Data Sheet, Rev. 2
Freescale Semiconductor
PRELIMINARY
153
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