MC9S08LC60 Datasheet, PDF (307/358 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 17 Development Support
17.2.3 BDC Commands
BDC commands are sent serially from a host computer to the BKGD pin of the target HCS08 MCU. All
commands and data are sent MSB-first using a custom BDC communications protocol. Active background
mode commands require that the target MCU is currently in the active background mode while
non-intrusive commands may be issued at any time whether the target MCU is in active background mode
or running a user application program.
Table 17-1 shows all HCS08 BDC commands, a shorthand description of their coding structure, and the
meaning of each command.
Coding Structure Nomenclature
This nomenclature is used in Table 17-1 to describe the coding structure of the BDC commands.
Commands begin with an 8-bit hexadecimal command code in the host-to-target
direction (most significant bit first)
/ = separates parts of the command
d = delay 16 target BDC clock cycles
AAAA = a 16-bit address in the host-to-target direction
RD = 8 bits of read data in the target-to-host direction
WD = 8 bits of write data in the host-to-target direction
RD16 = 16 bits of read data in the target-to-host direction
WD16 = 16 bits of write data in the host-to-target direction
SS = the contents of BDCSCR in the target-to-host direction (STATUS)
CC = 8 bits of write data for BDCSCR in the host-to-target direction (CONTROL)
RBKP = 16 bits of read data in the target-to-host direction (from BDCBKPT breakpoint
register)
WBKP = 16 bits of write data in the host-to-target direction (for BDCBKPT breakpoint register)
Table 17-1. BDC Command Summary
Command
Mnemonic
SYNC
Active BDM/
Non-intrusive
Non-intrusive
Coding
Structure
n/a¹
ACK_ENABLE
Non-intrusive
D5/d
ACK_DISABLE
Non-intrusive
BACKGROUND
READ_STATUS
WRITE_CONTROL
READ_BYTE
Non-intrusive
Non-intrusive
Non-intrusive
Non-intrusive
D6/d
90/d
E4/SS
C4/CC
E0/AAAA/d/RD
Description
Request a timed reference pulse to
determine target BDC communication
speed
Enable acknowledge protocol. Refer to
Freescale document order no.
HCS08RMv1/D.
Disable acknowledge protocol. Refer to
Freescale document order no.
HCS08RMv1/D.
Enter active background mode if enabled
(ignore if ENBDM bit equals 0)
Read BDC status from BDCSCR
Write BDC controls in BDCSCR
Read a byte from target memory
MC9S08LC60 Series Advance Information Data Sheet, Rev. 2
Freescale Semiconductor
PRELIMINARY
307