MC9S08LC60 Datasheet, PDF (344/358 Pages) Freescale Semiconductor, Inc – Microcontrollers

Appendix A Electrical Characteristics
A.10.3 SPI Timing
Table A-12 and Figure A-16 through Figure A-19 describe the timing requirements for the SPI system.
Table A-12. SPI Timing
No.
Function
Operating frequency
Master
Slave
SCK period
1
Master
Slave
Enable lead time
2
Master
Slave
Enable lag time
3
Master
Slave
Clock (SCK) high or low time
4
Master
Slave
Data setup time (inputs)
5
Master
Slave
Data hold time (inputs)
6
Master
Slave
7 Slave access time
8 Slave MISO disable time
Data valid (after SCK edge)
9
Master
Slave
Data hold time (outputs)
10
Master
Slave
Rise time
11
Input
Output
Fall time
12
Input
Output
Symbol
Min
Max
f_op
t_SCK
t_Lead
t_Lag
f_Bus/2048
dc
2
4
1/2
1
1/2
1
f_Bus/2
f_Bus/4
2048
—
—
—
—
—
t_WSCK
t_SU
t_cyc – 30
t_cyc – 30
15
15
1024 t_cyc
—
—
—
t_HI
0
—
25
—
t_a
—
1
t_dis
—
1
t_v
—
25
—
25
t_HO
0
—
0
—
t_RI
—
t_cyc – 25
t_RO
—
25
t_FI
—
t_cyc – 25
t_FO
—
25
Unit
Hz
t_cyc
t_cyc
t_SCK
t_cyc
t_SCK
t_cyc
ns
ns
ns
ns
ns
ns
t_cyc
t_cyc
ns
ns
ns
ns
ns
ns
ns
ns
MC9S08LC60 Series Advance Information Data Sheet, Rev. 2
344
PRELIMINARY
Freescale Semiconductor