MC9S08LC60 Datasheet, PDF (87/358 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 6 Parallel Input/Output
6.2.3 Port B Registers
This section provides information about all registers and control bits associated with the parallel I/O ports.
The parallel I/O registers are located in page zero of the memory map.
Refer to tables in Chapter 4, “Memory” for the absolute address assignments for all parallel I/O registers.
This section refers to registers and control bits only by their names. A Freescale-provided equate or header
file normally is used to translate these names into the appropriate absolute addresses.
6.2.3.1 Port B Data Registers (PTBD)
Port B parallel I/O function is controlled by the data and data direction registers in this section.
7
R
PTBD7
W
6
PTBD6
5
PTBD5
4
PTBD4
3
PTBD3
2
PTBD2¹
1
PTBD1
Reset
0
0
0
0
0
0
0
Figure 6-10. Port B Data Register (PTBD)
1 _{Reads of PTBD2 always return the contents of PTBD2, regardless of the value stored in the bit PTBDD2}
0
PTBD0
0
Table 6-6. PTBD Field Descriptions
Field
Description
7:0
PTBD[7:0]
Port B Data Register Bits — For port B pins that are inputs, reads return the logic level on the pin. For port B
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port B pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTBD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.
MC9S08LC60 Series Advance Information Data Sheet, Rev. 2
Freescale Semiconductor
PRELIMINARY
87