MC9S08LC60 Datasheet, PDF (88/358 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 6 Parallel Input/Output
6.2.3.2 Port B Data Direction Registers (PTBDD)
7
R
PTBDD7
W
6
PTBDD6
5
PTBDD5
4
PTBDD4
3
PTBDD3
2
PTBDD2¹
Reset
0
0
0
0
0
0
Figure 6-13. Data Direction for Port B (PTBDD)
1 _{PTBDD2 has no effect on the output-only PTB2 pin.}
1
PTBDD1
0
0
PTBDD0
0
Table 6-7. PTBDD Field Descriptions
Field
Description
7:0
Data Direction for Port B Bits — These read/write bits control the direction of port B pins and what is read for
PTBDD[7:0] PTBD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port B bit n and PTBD reads return the contents of PTBDn.
6.2.4 Port B Control Registers
Associated with the parallel I/O ports is a set of registers located in the high page register space that operate
independently of the parallel I/O registers. These registers are used to control pullups, slew rate, and drive
strength for the associated pins and may be used in conjunction with the peripheral functions on these pins
for most modules.
The pins associated with Port B are controlled by the registers in this section. These registers control the
pin pullup, slew rate and drive strength of the Port B pins independent of the parallel I/O registers.
6.2.4.1 Internal Pullup Enable (PTBPE)
An internal pullup device can be enabled for each port pin by setting the corresponding bit in the pullup
enable register (PTBPEn). The pullup device is disabled if the pin is configured as an output by the parallel
I/O control logic or any shared peripheral function regardless of the state of the corresponding pullup
enable register bit. The pullup device is also disabled if the pin is controlled by an analog function.
MC9S08LC60 Series Advance Information Data Sheet, Rev. 2
88
PRELIMINARY
Freescale Semiconductor