MC9S08LC60 Datasheet, PDF (163/358 Pages) Freescale Semiconductor, Inc – Microcontrollers

Liquid Crystal Display Driver (S08LCDV1)
9.6 Application Information
Figure 9-18 is a programmer’s model of the LCD module. The programmer’s model groups the LCD
module register bit and bit field into functional groups. The model is a very high level illustration of the
LCD module showing the module’s functional hierarchy including initialization and runtime control.
Data Bus
LCD Segment Display and Blink Control
LCD Segment Energize
LCDRAM Mode Select
LCDBCTL
LCDDRMS = 0
Segment Energize
LCDRAM
FP[40:0]BP[3:0]
Clear Display
LCDMISC
LCDCLR
BLANK
Blink Enable
and Command
Blink LCDRAM
Mode Select
LCDBCTL
BLKMODE
LCDDRMS = 1
BLINK
Segment Blink
Enable
LCDRAM
FP[40:0]BP[3:0]
Shown with 7-segment
LCD glass hardware
(not all LCD pins used)
FP[40:0]
LCD GLASS PANEL
BP[3:0]
LCD Frame
Frequency
Interrupt
LCDCR1
LCDIEN
LCDMISC
LCDIF
External Crystal = 32.768 kHz
Internal Clock Generator
Initialization Options
Module Enable
LCDCR0
LCDEN
Input Clock Source
LCDCLKS
SOURCE
DIV16
CLKADJ[5:0]
Frame Frequency
LCDCR0
LCLK[2:0]
DUTY[1:0]
Blink Rate
LCDBCTL
BLKMODE
BRATE[2:0]
LCD Pin Enable
FPENR[5:0]
FP[40:0]EN
Power Options
LCDCR1
LCDCPMS
LCDCPEN
LCDMISC
BBYPASS
VSUPPLY[1:0]
HDRVBUF
Low Power
LCDCR1
LCDWAI
LCDSTP3
V_cap1
C_LCD
V_{LCD X}
V_LL3
V_LL2
V_LL1
V_cap2
LCD Power Pins
NOTE: Configured
for power using
internal V_DD
C_BYLCD
LCD charge pump capacitance
Figure 9-18. LCD Programmer’s Model Diagram
9.6.1 LCD Seven Segment Example Description
A description of the connection between the LCD module and a seven segment LCD character is illustrated
below to provide a basic example for a LPWAVE = 0 and 1/3 duty cycle LCD implementation. The
example use backplane pins (BP0, BP1, BP2) and frontplace pins (FP0, FP1, and FP2). LCDRAM
contents and output waveforms are also shown. Output waveforms are illustrated in Figure 9-19 and
Figure 9-20.
MC9S08LC60 Series Advance Information Data Sheet, Rev. 2
Freescale Semiconductor
PRELIMINARY
163