MC9S08LC60 Datasheet, PDF (139/358 Pages) Freescale Semiconductor, Inc – Microcontrollers

Liquid Crystal Display Driver (S08LCDV1)
9.4.1.2 LCD Bias
Because a single frontplane driver is configured to drive more and more individual LCD segments, more
voltage levels are required to generate the appropriate waveforms to drive the segment. The LCD module
is designed to operate using the 1/3 bias mode.
Defined by Equation 9-5, the bias indicates the number of voltage levels used to power the LCD display.
1 / (voltage level – 1)
Eqn. 9-5
9.4.1.3 LCD Module Waveform Base Clock and Frame Frequency
The LCD module is designed to operate using a 32.768-kHz clock input. Two possible clock sources are
available to the LCD module has which are selectable by configuration of the SOURCE bit in the
LCDCLKS register. The two clock sources include:
• External crystal (SOURCE = 0)
• Internal ICG (SOURCE = 1)
Figure 9-10 shows the LCD clock tree. The clock tree shows the two possible clock sources and shows the
LCD frame frequency and blink frequency clock source. The LCD blink frequency is discussed in
Section 9.4.3.2, “Blink Frequency.”
SOURCE
DIV16
CLKADJ[5:0]
LCDCLK
LCLK[2:0]
BRATE[2:0]
Internal Clock
÷16
External Clock = 32.768 kHz
÷(1+CLKADJ[5:0])
÷8
÷(2^LCLK[2:0])
÷(2^5+BRATE[2:0])
÷2^{(1+CPCADJ[1:0])}
÷2
÷2
÷6
LCD Charge Pump Clock
Source
CPCADJ[1:0]
Blink Rate
Source
LCD Base Frequency
Source
Figure 9-10. LCD Clock Tree
Because the clock sources may not be approximately 32.768 kHz, the DIV16 bit and CLKADJ[5:0] bit
field are provided as a clock divider mechanism that can be used to make LCD module clock source
adjustments in order to achieve the required 32.768-kHz LCD module clock input, LCDCLK. Table 9-14
provides calculations of LCDCLK using different values of DIV16 and CLKADJ[5:0] for a range of clock
inputs frequencies. Using an external 32.768-kHz clock input is required for reduced power consumption
applications.
MC9S08LC60 Series Advance Information Data Sheet, Rev. 2
Freescale Semiconductor
PRELIMINARY
139