MC68HC000RC12 Datasheet, PDF (90/189 Pages) Freescale Semiconductor, Inc – 8-/16-/32-Bit Microprocessors User’s Manual

Freescale Semiconductor, Inc.
D15
IGNORED
Where:
v7 is the MSB of the vector number
v0 is the LSB of the vector number
D8
D7
D0
v7
v6
v5
v4
v3
v2
v1
v0
Figure 6-2. Peripheral Vector Number Format
A31
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
ALL ZEROES
v7
v6
v5
v4
v3
v2
v1
v0
0
0
Figure 6-3. Address Translated from 8-Bit Vector Number
(MC68000, MC68HC000, MC68HC001, MC68EC000, and MC68008)
31
0
CONTENTS OF VECTOR BASE REGISTER
31
ALL ZEROES
10
0
v7 v6 v5 v4 v3 v2 v1 v0 0 0
+
EXCEPTION VECTOR
ADDRESS
Figure 6-4. Exception Vector Address Calculation (MC68010)
The actual address on the address bus is truncated to the number of address bits
available on the bus of the particular implementation of the M68000 architecture. In all
processors except the MC68008, this is 24 address bits. (A0 is implicitly encoded in the
data strobes.) In the MC68008, the address is 20 or 22 bits in length. The memory map for
exception vectors is shown in Table 6-2.
The vector table, Table 6-2, is 512 words long (1024 bytes), starting at address 0
(decimal) and proceeding through address 1023 (decimal). The vector table provides 255
unique vectors, some of which are reserved for trap and other system function vectors. Of
the 255, 192 are reserved for user interrupt vectors. However, the first 64 entries are not
protected, so user interrupt vectors may overlap at the discretion of the systems designer.
6.2.2 Kinds of Exceptions
Exceptions can be generated by either internal or external causes. The externally
generated exceptions are the interrupts, the bus error, and reset. The interrupts are
MOTOROLA
M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL
6-5
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