MC68HC000RC12 Datasheet, PDF (137/189 Pages) Freescale Semiconductor, Inc – 8-/16-/32-Bit Microprocessors User’s Manual

Freescale Semiconductor, Inc.
Table 9-15. Conditional Instruction Execution Times
Instruction
Bcc
BRA
BSR
DBcc
Displacement
Byte
Word
Byte
Word
Byte
Word
cc true
cc false
Branch Taken
10(2/0)
10(2/0)
10(2/0)
10(2/0)
18(2/2)
18(2/2)
—
10(2/0)
Branch Not Taken
6(1/0)
10(2/0)
—
—
—
—
10(2/0)
16(3/0)
9.9 JMP, JSR, LEA, PEA, AND MOVEM INSTRUCTION
EXECUTION TIMES
Table 9-16 lists the timing data for the jump (JMP), jump to subroutine (JSR), load
effective address (LEA), push effective address (PEA), and move multiple registers
(MOVEM) instructions. The total number of clock periods, the number of read cycles, and
the number of write cycles are shown in the previously described format.
Table 9-16. JMP, JSR, LEA, PEA, and MOVEM Instruction Execution Times
Instruction
JMP
JSR
LEA
PEA
MOVEM
M→R
Size
—
—
—
—
Word
Long
MOVEM
R→M
Word
Long
MOVES
M→R
MOVES
R→M
Byte/
Word
Long
Byte/
Word
Long
(An)
8(2/0)
16 (2/2)
4(1/0)
12 (1/2)
12+4n
(3+n/0)
24+8n
(3+2n/0)
8+4n
(2/n)
8+8n
(2/2n)
18 (3/0)
(An)+
—
—
—
—
12+4n
(3+n/0)
12+8n
(3+2n/0)
—
—
—
—
20 (3/0)
–(An)
—
—
—
—
—
—
—
—
8+4n
(2/n)
8+8n
(2/2n)
20 (3/0)
22 (4/0) 24 (4/0) 24 (4/0)
18 (2/1) 20 (2/1) 20 (2/1)
22 (2/2) 24 (2/2) 24 (2/2)
(d ₁₆ ,An)
10 (2/0)
18 (2/2)
8(2/0)
16 (2/2)
16+4n
(4+n/0)
16+8n
(4+2n/0)
12+4n
(3/n)
12+8n
(3/2n)
20 (4/0)
24 (5/0)
20 (3/1)
24 (3/2)
(d _8,An,Xn)+
14 (3/0)
22 (2/2)
12 (2/0)
20 (2/2)
18+4n
(4+n/0)
18+8n
(4+2n/0)
14+4n
(3/n)
14+8n
(3/2n)
24 (4/0)
28 (5/0)
24 (3/1)
28 (3/2)
(xxx) W
10 (2/0)
18 (2/2)
8(2/0)
16 (2/2)
16+4n
(4+n/0)
16+8n
(4+2n/0)
12+4n
(3/n)
12+8n
(3/2n)
20 (4/0)
24 (5/0)
20 (3/1)
24 (3/2)
(xxx).L
12 (3/0)
20 (3/2)
12 (3/0)
20 (3/2)
20+4n
(5+n/0)
20+8n
(5+2n/0)
16+4n
(4/n)
16+8n
(4/2n)
24 (5/0)
28 (6/0)
24 (4/1)
28 (4/2)
(d ₈ PC)
10 (2/0)
18 (2/2)
8(2/0)
16 (2/2)
16+4n
(4+n/0)
16+8n
(4+2n/0)
—
—
—
—
(d ₁₆ , PC, Xn)*
14 (3/0)
22 (2/2)
12 (2/0)
20 (2/2)
18+4n
(4+n/0)
18+8n
(4+2n/0)
—
—
—
—
n is the number of registers to move.
*The size of the index register (Xn) does not affect the instruction's execution time.
9.10 MULTIPRECISION INSTRUCTION EXECUTION TIMES
Table 9-17 lists the timing data for multiprecision instructions. The numbers of clock
periods include the times to fetch both operands, perform the operations, store the results,
9-10
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
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