MC68HC000RC12 Datasheet, PDF (131/189 Pages) Freescale Semiconductor, Inc – 8-/16-/32-Bit Microprocessors User’s Manual

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Table 9-4. Move Long Instruction Execution Times
Destination
Source
Dn
An
(An) (An)+ –(An) (d16, An)
Dn
4(1/0) 4(1/0) 12(1/2) 12(1/2) 14(1/2) 16(2/2)
An
4(1/0) 4(1/0) 12(1/2) 12(1/2) 14(1/2) 16(2/2)
(An)
12(3/0) 12(3/0) 20(3/2) 20(3/2) 20(3/2) 24(4/2)
(An)+
–(An)
(d _16, An)
(d _8, An, Xn)*
(xxx).W
(xxx).L
12(3/0)
14(3/0)
16(4/0)
18(4/0)
16(4/0)
20(5/0)
12(3/0)
14(3/0)
16(4/0)
18(4/0)
16(4/0)
20(5/0)
20(3/2)
22(3/2)
24(4/2)
26(4/2)
24(4/2)
28(5/2)
20(3/2)
22(3/2)
24(4/2)
26(4/2)
24(4/2)
28(5/2)
20(3/2)
22(3/2)
24(4/2)
26(4/2)
24(4/2)
28(5/2)
24(4/2)
26(4/2)
28(5/2)
30(5/2)
28(5/2)
32(6/2)
(d _16, PC)
16(4/0)
(d _8, PC, Xn)* 18(4/0)
#<data>
12(3/0)
16(4/0)
18(4/0)
12(3/0)
24(4/2)
26(4/2)
20(3/2)
24(4/2)
26(4/2)
20(3/2)
24(4/2)
26(4/2)
20(3/2)
28(5/2)
30(5/2)
24(4/2)
*The size of the index register (Xn) does not affect execution time.
(d8, An, Xn)*
18(2/2)
18(2/2)
26(4/2)
26(4/2)
28(4/2)
30(5/2)
32(5/2)
30(5/2)
34(6/2)
30(5/2)
32(5/2)
26(4/2)
(xxx).W
16(2/2)
16(2/2)
24(4/2)
24(4/2)
26(4/2)
28(5/2)
30(5/2)
28(5/2)
32(6/2)
28(5/2)
30(5/2)
24(4/2)
(xxx).L
20(3/2)
20(3/2)
28(5/2)
28(5/2)
30(5/2)
32(6/2)
34(6/2)
32(6/2)
36(7/2)
32(5/2)
34(6/2)
28(5/2)
Source
Dn
An
(An)
(An)+
–(An)
Table 9-5. Move Long Instruction Loop Mode Execution Times
Loop Continued
Valid Count, cc False
(An)
14(0/2)
14(0/2)
22(2/2)
22(2/2)
24(2/2)
(An)+
14(0/2)
14(0/2)
22(2/2)
22(2/2)
24(2/2)
–(An)
—
—
24(2/2)
24(2/2)
26(2/2)
Loop Terminated
Valid count, cc True
Expired Count
Destination
(An)
(An)+
–(An)
(An)
(An)+
–(An)
20(2/2)
20(2/2)
28(4/2)
20(2/2)
20(2/2)
28(4/2)
—
—
30(4/2)
18(2/2)
18(2/2)
24(4/2)
18(2/2)
18(2/2)
24(4/2)
—
—
26(4/2)
28(4/2)
30(4/2)
28(4/2)
30(4/2)
30(4/2)
32(4/2)
24(4/2)
26(4/2)
24(4/2)
26(4/2)
26(4/2)
28(4/2)
9.3 STANDARD INSTRUCTION EXECUTION TIMES
The numbers of clock periods shown in tables 9-6 and 9-7 indicate the times required to
perform the operations, store the results, and read the next instruction. The total number
of clock periods, the number of read cycles, and the number of write cycles are shown in
the previously described format. The number of clock periods, the number of read cycles,
and the number of write cycles, respectively, must be added to those of the effective
address calculation where indicated by a plus sign (+).
In Tables 9-6 and 9-7, the following notation applies:
An — Address register operand
Sn — Data register operand
ea — An operand specified by an effective address
M — Memory effective address operand
9-4
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
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