MC68HC000RC12 Datasheet, PDF (165/189 Pages) Freescale Semiconductor, Inc – 8-/16-/32-Bit Microprocessors User’s Manual

Freescale Semiconductor, Inc.
Num
Characteristic
8 MHz
10 MHz
12.5 MHz 16.67 MHz 20 MHz Unit
Min Max Min Max Min Max Min Max Min Max
29 AS, DS Negated to Data-In Invalid 0 — 0 — 0 — 0 — 0 — ns
(Hold Time on Read)
29A AS, DS Negated to Data-In High
Impedance
— 187 — 150 — 120 — 90 — 75 ns
30 AS, DS Negated to BERR
0 — 0 — 0 — 0 — 0 — ns
Negated
312, ⁵ DTACK Asserted to Data-In Valid — 90 — 65 — 50 — 50 — 42 ns
(Setup Time)
32 HALT and RESET Input Transition 0 150 0 150 0 150 0 150 0 150 ns
Time
33 Clock High to BG Asserted
— 35 — 35 — 35 0 30 0 25 ns
34 Clock High to BG Negated
— 35 — 35 — 35 0 30 0 25 ns
35 BR Asserted to BG Asserted
367 BR Negated to BG Negated
1.5 3.5 1.5 3.5 1.5 3.5 1.5 3.5 1.5 3.5 Clks
1.5 3.5 1.5 3.5 1.5 3.5 1.5 3.5 1.5 3.5 Clks
38 BG Asserted to Control, Address, — 55 — 55 — 55 — 50 — 42 ns
Data Bus High Impedance (AS
Negated)
39 BG Width Negated
1.5
1.5
1.5
1.5
1.5 — Clks
44 AS, DS Negated to VPA Negated 0 55 0 55 0 55 0 50 0 42 ns
475 Asynchronous Input Setup Time
5
—
5
—
5
—
5
— 5 — ns
482, ³ BERR Asserted to DTACK
Asserted
20 — 20 — 20 — 10 — 10 — ns
53 Data-Out Hold from Clock High
0
—
0
—
0
—
0
— 0 — ns
55 R/ W Asserted to Data Bus
Impedance Change
30 — 20 — 10 — 0 — 0 — ns
564 HALT/RESET Pulse Width
10 — 10 — 10 — 10 — 10 — Clks
587 BR Negated to AS, DS, R/ W
Driven
1.5 — 1.5 — 1.5 — 1.5 — 1.5 — Clks
58A7 BR Negated to FC, VMA Driven
1
—
1
—
1
—
1
— 1 — Clks
NOTES:1. For a loading capacitance of less than or equal to 50 pF, subtract 5 ns from the value given in the
maximum columns.
2. Actual value depends on clock period.
3.I f #47 is satisfied for both DTACK and BERR , #48 may be ignored. In the absence of DTACK, BERR is an
asynchronous input using the asynchronous input setup time (#47).
4. For power-up, the MC68EC000 must be held in the reset state for 520 clocks to allow stabilization of on-
chip circuitry. After the system is powered up, #56 refers to the minimum pulse width required to
reset the processor.
5. If the asynchronous input setup time (#47) requirement is satisfied for DTACK, the DTACK -asserted to data
setup time (#31) requirement can be ignored. The data must only satisfy the data-in to clock low
setup time (#27) for the following clock cycle.
6. When AS and R/W are equally loaded (±20;pc), subtract 5 ns from the values given in these columns.
7. The minimum value must be met to guarantee proper operation. If the maximum value is exceeded,
BG may be reasserted.
8. DS is used in this specification to indicate UDS and LDS .
MOTOROLA
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
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