MC68HC000RC12 Datasheet, PDF (52/189 Pages) Freescale Semiconductor, Inc – 8-/16-/32-Bit Microprocessors User’s Manual

Freescale Semiconductor, Inc.
CLK
FC2–FC0
A23–A1
S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7
A0*
AS
UDS
LDS
R/W
DTACK
D15–D8
D7–D0
*INTERNAL SIGNAL ONLY
WORD WRITE
ODD BYTE WRITE
EVEN BYTE WRITE
Figure 5-7. Word and Byte Write-Cycle Timing Diagram
The descriptions of the eight states of a write cycle are as follows:
STATE 0 The write cycle starts in S0. The processor places valid function codes on
FC2–FC0 and drives R/W high (if a preceding write cycle has left R/W low).
STATE 1 Entering S1, the processor drives a valid address on the address bus.
STATE 2 On the rising edge of S2, the processor asserts AS and drives R/W low.
STATE 3 During S3, the data bus is driven out of the high-impedance state as the
data to be written is placed on the bus.
STATE 4
At the rising edge of S4, the processor asserts U D S , or LDS. The
processor waits for a cycle termination signal (DTACK or BERR) or VPA, an
M6800 peripheral signal. When VPA is asserted during S4, the cycle
becomes a peripheral cycle (refer to Appendix B M6800 Peripheral
Interface. If neither termination signal is asserted before the falling
edge at the end of S4, the processor inserts wait states (full clock cycles)
until either DTACK or BERR is asserted.
STATE 5 During S5, no bus signals are altered.
STATE 6 During S6, no bus signals are altered.
5-6
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
MOTOROLA
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