MC68HC000RC12 Datasheet, PDF (72/189 Pages) Freescale Semiconductor, Inc – 8-/16-/32-Bit Microprocessors User’s Manual

Freescale Semiconductor, Inc.
NOTE
In the MC68010, if a read-modify-write operation terminates in
a bus error, the processor reruns the entire read-modify-write
operation when the RTE instruction at the end of the bus error
handler returns control to the instruction in error. The
processor reruns the entire operation whether the error
occurred during the read or write portion.
5.4.2 Retrying The Bus Cycle
The assertion of the bus error signal during a bus cycle in which HALT is also asserted by
an external device initiates a retry operation. Figure 5-27 is a timing diagram of the retry
operation. The delayed BERR signal in the MC68010 also initiates a retry operation when
HALT is asserted by an external device. Figure 5-28 shows the timing of the delayed
operation.
S0 S2 S4 S6 S8
CLK
FC2-FC0
A23–A1
AS
LDS/UDS
R/W
DTACK
D15–D0
BERR
HALT
READ
≥ 1 CLOCK PERIOD
HALT
S0 S2 S4 S6
RETRY
Figure 5-27. Retry Bus Cycle Timing Diagram
5-26
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
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