MC68HC000RC12 Datasheet, PDF (112/189 Pages) Freescale Semiconductor, Inc – 8-/16-/32-Bit Microprocessors User’s Manual

Freescale Semiconductor, Inc.
7.7 BIT MANIPULATION INSTRUCTION EXECUTION TIMES
Table 7-9 lists the timing data for the bit manipulation instructions. The total number of
clock periods, the number of read cycles, and the number of write cycles are shown in the
previously described format. The number of clock periods, the number of read cycles, and
the number of write cycles, respectively, must be added to those of the effective address
calculation where indicated by a plus sign (+).
Table 7-9. Bit Manipulation Instruction Execution Times
Dynamic
Instruction
BCHG
Size
Byte
Long
Register
—
12(2/0)*
Memory
12(2/1)+
—
BCLR
BSET
BTST
Byte
Long
Byte
Long
Byte
Long
—
14(2/0)*
—
12(2/0)*
—
10(2/0)
12(2/1)+
—
12(2/1)+
—
8(2/0)+
+Add effective address calculation time.
* Indicates maximum value; data addressing mode only.
Static
Register
—
20(4/0)*
Memory
20(4/1)+
—
—
22(4/0)*
—
20(4/0)*
—
18(4/0)
20(4/1)+
—
20(4/1)+
—
16(4/0)+
—
7.8 CONDITIONAL INSTRUCTION EXECUTION TIMES
Table 7-10 lists the timing data for the conditional instructions. The total number of clock
periods, the number of read cycles, and the number of write cycles are shown in the
previously described format. The number of clock periods, the number of read cycles, and
the number of write cycles, respectively, must be added to those of the effective address
calculation where indicated by a plus sign (+).
Table 7-10. Conditional Instruction Execution Times
Instruction
Displacement
Trap or Branch
Taken
Bcc
BRA
Byte
Word
Byte
Word
18(4/0)
18(4/0)
18(4/0)
18(4/0)
BSR
DBcc
CHK
TRAP
Byte
Word
CC True
CC False
—
—
34(4/4)
34(4/4)
—
18(4/0)
68(8/6)+*
62(8/6)
TRAPV
—
66(10/6)
+Add effective address calculation time for word operand.
* Indicates maximum base value.
Trap or Branch
Not Taken
12(2/0)
20(4/0)
—
—
—
—
20(4/0)
26(6/0)
14(2/0)
—
8(2/0)
MOTOROLA
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
7-7
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