MC68HC000RC12 Datasheet, PDF (126/189 Pages) Freescale Semiconductor, Inc – 8-/16-/32-Bit Microprocessors User’s Manual

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Table 8-12. Miscellaneous Instruction Execution Times
Instruction
Size
ANDI to CCR
Byte
ANDI to SR
Word
CHK (No Trap)
—
EORI to CCR
Byte
EORI to SR
Word
ORI to CCR
Byte
ORI to SR
Word
MOVE from SR
—
MOVE to CCR
—
MOVE to SR
—
EXG
—
EXT
Word
Long
LINK
—
MOVE from USP
—
MOVE to USP
—
NOP
—
RESET
—
RTE
—
RTR
—
RTS
—
STOP
—
SWAP
—
TRAPV
—
UNLK
—
+Add effective address calculation time.
Register
20(3/0)
20(3/0)
10(1/0)+
20(3/0)
20(3/0)
20(3/0)
20(3/0)
6(1/0)
12(1/0)
12(2/0)
6(1/0)
4(1/0)
4(1/0)
16(2/2)
4(1/0)
4(1/0)
4(1/0)
132(1/0)
20(5/0)
20(2/0)
16(4/0)
4(0/0)
4(1/0)
4(1/0)
12(3/0)
Memory
—
—
—
—
—
—
—
8(1/1)+
12(1/0)+
12(2/0)+
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Table 8-13. Move Peripheral Instruction Execution Times
Instruction
MOVEP
Size
Word
Long
Register → Memory
16(2/2)
24(2/4)
Memory → Register
16(4/0)
24(6/0)
8.12 EXCEPTION PROCESSING EXECUTION TIMES
Table 8-14 lists the timing data for exception processing. The numbers of clock periods
include the times for all stacking, the vector fetch, and the fetch of the first instruction of
8-10
MC68000 8-/16-/32-MICROPROCESSORS UISER'S MANUAL
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