MC68HC000RC12 Datasheet, PDF (74/189 Pages) Freescale Semiconductor, Inc – 8-/16-/32-Bit Microprocessors User’s Manual

Freescale Semiconductor, Inc.
S0 S2 S4 S6
CLK
FC2–FC0
A23–A1
AS
UDS
LDS
R/W
DTACK
D0–D15
BERR
HALT
READ
S0 S2 S4 S6
HALT
RETRY
Figure 5-29. Halt Operation Timing Diagram
While the processor is halted, the address bus and the data bus signals are placed in the
high-impedance state. Bus arbitration is performed as usual. Should a bus error occur
while HALT is asserted, the processor performs the retry operation previously described.
The single-step mode is derived from correctly timed transitions of HALT. HALT is negated
to allow the processor to begin a bus cycle, then asserted to enter the halt mode when the
cycle completes. The single-step mode proceeds through a program one bus cycle at a
time for debugging purposes. The halt operation and the hardware trace capability allow
tracing of either bus cycles or instructions one at a time. These capabilities and a software
debugging package provide total debugging flexibility.
5.4.4 Double Bus Fault
When a bus error exception occurs, the processor begins exception processing by
stacking information on the supervisor stack. If another bus error occurs during exception
processing (i.e., before execution of another instruction begins) the processor halts and
asserts HALT. This is called a double bus fault. Only an external reset operation can
restart a processor halted due to a double bus fault.
A retry operation does not initiate exception processing; a bus error during a retry
operation does not cause a double bus fault. The processor can continue to retry a bus
cycle indefinitely if external hardware requests.
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M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
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