MC68HC000RC12 Datasheet, PDF (85/189 Pages) Freescale Semiconductor, Inc – 8-/16-/32-Bit Microprocessors User’s Manual

Freescale Semiconductor, Inc.
Parameter #47 of Section 10 Electrical Characteristics is the asynchronous input setup
time. Signals that meet parameter #47 are guaranteed to be recognized at the next falling
edge of the system clock. However, signals that do not meet parameter #47 are not
guaranteed to be recognized. In addition, if DTACK is recognized on a falling edge, valid
data is latched into the processor (during a read cycle) on the next falling edge, provided
the data meets the setup time required (parameter #27). When parameter #27 has been
met, parameter #31 may be ignored. If DTACK is asserted with the required setup time
before the falling edge of S4, no wait states are incurred, and the bus cycle runs at its
maximum speed of four clock periods.
The late BERR in an MC68010 that is operating in a synchronous mode must meet setup
time parameter #27A. That is, when BERR is asserted after DTACK, BERR must be
asserted before the falling edge of the clock, one clock cycle after DTACK is recognized.
Violating this requirement may cause the MC68010 to operate erratically.
MOTOROLA
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
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