MC68HC000RC12 Datasheet, PDF (77/189 Pages) Freescale Semiconductor, Inc – 8-/16-/32-Bit Microprocessors User’s Manual

Freescale Semiconductor, Inc.
Table 5-1. DTACK, BERR, and HALT Assertion Results
Case Control
No. Signal
Asserted on
Rising Edge
of State
MC68000/MC68HC000/001
EC000/MC68008 Results
MC68010 Results
N N+2
1 DTACK A
S Normal cycle terminate and continue. Normal cycle terminate and continue.
BERR NA NA
HALT NA
X
2 DTACK A
S Normal cycle terminate and halt.
BERR NA NA Continue when HALT negated.
HALT A/S
S
Normal cycle terminate and halt.
Continue when HALT negated.
3 DTACK X
X Terminate and take bus error trap.
BERR
A
S
HALT NA NA
Terminate and take bus error trap.
4 DTACK A
S Normal cycle terminate and continue. Terminate and take bus error trap.
BERR NA
A
HALT NA NA
5 DTACK X
BERR
A
HALT A/S
X Terminate and retry when HALT
S removed.
S
Terminate and retry when HALT
removed.
6 DTACK A
BERR NA
HALT NA
S Normal cycle terminate and continue. Terminate and retry when HALT
A
removed.
A
LEGEND:
N — The number of the current even bus state (e.g., S4, S6, etc.)
A — Signal asserted in this bus state
NA — Signal not asserted in this bus state
X — Don't care
S — Signal asserted in preceding bus state and remains asserted in this state
NOTE: All operations are subject to relevant setup and hold times.
The negation of BERR and HALT under several conditions is shown in Table 5-6. (DTACK
is assumed to be negated normally in all cases; for reliable operation, both DTACK and
BERR should be negated when address strobe is negated).
EXAMPLE A:
A system uses a watchdog timer to terminate accesses to unused address space. The
timer asserts BERR after timeout (case 3).
EXAMPLE B:
A system uses error detection on random-access memory (RAM) contents. The system
designer may:
1. Delay DTACK until the data is verified. If data is invalid, return BERR and HALT
simultaneously to retry the error cycle (case 5).
2. Delay DTACK until the data is verified. If data is invalid, return BERR at the same
time as DTACK (case 3).
3. For an MC68010, return DTACK before data verification. If data is invalid, assert
BERR and HALT to retry the error cycle (case 6).
MOTOROLA
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
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