MC68HC000RC12 Datasheet, PDF (54/189 Pages) Freescale Semiconductor, Inc – 8-/16-/32-Bit Microprocessors User’s Manual

Freescale Semiconductor, Inc.
CLK
A23–A1
S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19
AS
UDS OR LDS
R/W
DTACK
D15–D8
FC2–FC0
INDIVISIBLE CYCLE
Figure 5-9. Read-Modify-Write Cycle Timing Diagram
The descriptions of the read-modify-write cycle states are as follows:
STATE 0 The read cycle starts in S0. The processor places valid function codes on
FC2–FC0 and drives R/W high to identify a read cycle.
STATE 1 Entering S1, the processor drives a valid address on the address bus.
STATE 2 On the rising edge of S2, the processor asserts AS and UDS, or LDS.
STATE 3 During S3, no bus signals are altered.
STATE 4
During S4, the processor waits for a cycle termination signal (DTACK or
BERR) or VPA, an M6800 peripheral signal. When VPA is asserted during
S4, the cycle becomes a peripheral cycle (refer to Appendix B M6800
Peripheral Interface). If neither termination signal is asserted before the
falling edge at the end of S4, the processor inserts wait states (full clock
cycles) until either DTACK or BERR is asserted.
STATE 5 During S5, no bus signals are altered.
STATE 6 During S6, data from the device are driven onto the data bus.
STATE 7
On the falling edge of the clock entering S7, the processor accepts data
from the device and negates U D S , and LDS. The device negates
DTACK or BERR at this time.
STATES 8–11
The bus signals are unaltered during S8–S11, during which the arithmetic
logic unit makes appropriate modifications to the data.
5-8
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com