MC68HC000RC12 Datasheet, PDF (111/189 Pages) Freescale Semiconductor, Inc – 8-/16-/32-Bit Microprocessors User’s Manual

Freescale Semiconductor, Inc.
Table 7-7. Single Operand Instruction
Execution Times
Instruction
Size
Register
CLR
NBCD
Byte
Word
Long
Byte
8(2/0)
8(2/0)
10(2/0)
10(2/0)
NEG
Byte
Word
Long
8(2/0)
8(2/0)
10(2/0)
NEGX
NOT
Scc
Byte
Word
Long
Byte
Word
Long
Byte, False
Byte, True
8(2/0)
8(2/0)
10(2/0)
8(2/0)
8(2/0)
10(2/0)
8(2/0)
10(2/0)
TAS
Byte
8(2/0)
TST
Byte
8(2/0)
Word
8(2/0)
Long
8(2/0)
+Add effective address calculation time.
Memory
12(2/1)+
16(2/2)+
24(2/4)+
12(2/1)+
12(2/1)+
16(2/2)+
24(2/4)+
12(2/1)+
16(2/2)+
24(2/4)+
12(2/1)+
16(2/2)+
24(2/4)+
12(2/1)+
12(2/1)+
14(2/1)+
8(2/0)+
8(2/0)+
8(2/0)+
7.6 SHIFT/ROTATE INSTRUCTION EXECUTION TIMES
Table 7-8 lists the timing data for the shift and rotate instructions. The total number of
clock periods, the number of read cycles, and the number of write cycles are shown in the
previously described format. The number of clock periods, the number of read cycles, and
the number of write cycles, respectively, must be added to those of the effective address
calculation where indicated by a plus sign (+).
Table 7-8. Shift/Rotate Instruction Execution Times
Instruction
ASR, ASL
LSR, LSL
Size
Byte
Word
Long
Byte
Word
Long
Register
10+2n (2/0)
10+2n (2/0)
12+n2 (2/0)
10+2n (2/0)
10+2n (2/0)
12+n2 (2/0)
Memory
—
16(2/2)+
—
—
16(2/2)+
—
ROR, ROL
ROXR, ROXL
Byte
Word
Long
Byte
Word
Long
10+2n (2/0)
10+2n (2/0)
12+n2 (2/0)
10+2n (2/0)
10+2n (2/0)
12+n2 (2/0)
—
16(2/2)+
—
—
16(2/2)+
—
+Add effective address calculation time for word operands.
n is the shift count.
7-6
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
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