MC68HC000RC12 Datasheet, PDF (59/189 Pages) Freescale Semiconductor, Inc – 8-/16-/32-Bit Microprocessors User’s Manual

Freescale Semiconductor, Inc.
PROCESSOR
GRANT BUS ARBITRATION
1) ASSERT BUS GRANT (BG)
REQUESTING DEVICE
REQUEST THE BUS
1) ASSERT BUS REQUEST (BR)
OPERATE AS BUS MASTER
1) EXTERNAL ARBITRATION DETER-
MINES NEXT BUS MASTER
2) NEXT BUS MASTER WAITS FOR
CURRENT CYCLE TO COMPLETE
ACKNOWLEDGE RELEASE OF
BUS MASTERSHIP
1) NEGATE BUS GRANT (BG)
RELEASE BUS MASTERSHIP
1) NEGATE BUS REQUEST (BR)
REARBITRATE OR RESUME
PROCESSOR OPERATION
Figure 5-14. 2-Wire Bus Arbitration Cycle Flowchart
CLK
FC2–FC0
A23–A1
AS
LDS/ UDS
R/W
DTACK
D15–D0
BR
BG
BGACK
PROCESSOR
DMA DEVICE
PROCESSOR
DMA DEVICE
Figure 5-15. 3-Wire Bus Arbitration Timing Diagram
(Not Applicable to 48-Pin MC68008 or MC68EC000)
MOTOROLA
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
5-13
For More Information On This Product,
Go to: www.freescale.com