MC68HC000RC12 Datasheet, PDF (129/189 Pages) Freescale Semiconductor, Inc – 8-/16-/32-Bit Microprocessors User’s Manual

Freescale Semiconductor, Inc.
9.1 OPERAND EFFECTIVE ADDRESS CALCULATION TIMES
Table 9-1 lists the numbers of clock periods required to compute the effective addresses
for instructions. The totals include fetching any extension words, computing the address,
and fetching the memory operand. The total number of clock periods, the number of read
cycles, and the number of write cycles (zero for all effective address calculations) are
shown in the previously described format.
Table 9-1. Effective Address Calculation Times
Addressing Mode
Register
Dn
Data Register Direct
An
Address Register Direct
Memory
(An)
(An)+
Address Register Indirect
Address Register Indirect with Postincrement
–(An)
(d _16, An)
(d _8, An, Xn)*
(xxx).W
Address Register Indirect with Predecrement
Address Register Indirect with Displacement
Address Register Indirect with Index
Absolute Short
(xxx).L
(d _16, PC)
(d _8, PC, Xn)*
#<data>
Absolute Long
Program Counter Indirect with Displacement
Program Counter Indirect with Index
Immediate
*The size of the index register (Xn) does not affect execution time.
Byte, Word
Fetch
No Fetch
0(0/0)
—
0(0/0)
—
4(1/0)
4(1/0)
6(1/0)
8(2/0)
10(2/0)
8(2/0)
12(3/0)
8(2/0)
10(2/0)
4(1/0)
2(0/0)
4(0/0)
4(0/0)
4(0/0)
8(1/0)
4(1/0)
8(2/0)
—
—
—
Long
Fetch
No Fetch
0(0/0)
—
0(0/0)
—
8(2/0)
8(2/0)
10(2/0)
12(3/0)
14(3/0)
12(3/0)
16(4/0)
12(3/0)
14(3/0)
8(2/0)
2(0/0)
4(0/0)
4(0/0)
4(1/0)
8(1/0)
4(1/0)
8(2/0)
—
—
—
9.2 MOVE INSTRUCTION EXECUTION TIMES
Tables 9-2, 9-3, 9-4, and 9-5 list the numbers of clock periods for the move instructions.
The totals include instruction fetch, operand reads, and operand writes. The total number
of clock periods, the number of read cycles, and the number of write cycles are shown in
the previously described format.
9-2
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
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