MC68HC000RC12 Datasheet, PDF (25/189 Pages) Freescale Semiconductor, Inc – 8-/16-/32-Bit Microprocessors User’s Manual

Freescale Semiconductor, Inc.
Table 2-2. Instruction Set Summary (Sheet 1 of 4)
Opcode
ABCD
Operation
Source10 + Destination10 + X → Destination
ADD
Source + Destination → Destination
ADDA
ADDI
ADDQ
ADDX
Source + Destination → Destination
Immediate Data + Destination → Destination
Immediate Data + Destination → Destination
Source + Destination + X → Destination
AND
Source Λ Destination → Destination
ANDI
Immediate Data Λ Destination → Destination
ANDI to CCR Source Λ CCR → CCR
ANDI to SR If supervisor state
then Source Λ SR → SR
else TRAP
ASL, ASR Destination Shifted by <count> → Destination
Bcc
BCHG
BCLR
BKPT
BRA
BSET
BSR
BTST
If (condition true) then PC + d → PC
~ (<number> of Destination) → Z;
~ (<number> of Destination) → <bit number> of Destination
~ (<bit number> of Destination) → Z;
0 → <bit number> of Destination
Run breakpoint acknowledge cycle;
TRAP as illegal instruction
PC + d → PC
~ (<bit number> of Destination) → Z;
1 → <bit number> of Destination
SP – 4 → SP; PC → (SP); PC + d → PC
– (<bit number> of Destination) → Z;
CHK
CLR
CMP
CMPA
CMPI
CMPM
DBcc
If Dn < 0 or Dn > Source then TRAP
0 → Destination
Destination—Source → cc
Destination—Source
Destination —Immediate Data
Destination—Source → cc
If condition false then (Dn – 1 → Dn;
If Dn ≠ –1 then PC + d → PC)
Syntax
ABCD Dy,Dx
ABCD –(Ay), –(Ax)
ADD <ea>,Dn
ADD Dn,<ea>
ADDA <ea>,An
ADDI # <data>,<ea>
ADDQ # <data>,<ea>
ADDX Dy, Dx
ADDX –(Ay), –(Ax)
AND <ea>,Dn
AND Dn,<ea>
ANDI # <data>, <ea>
ANDI # <data>, CCR
ANDI # <data>, SR
ASd Dx,Dy
ASd # <data>,Dy
ASd <ea>
Bcc <label>
BCHG Dn,<ea>
BCHG # <data>,<ea>
BCLR Dn,<ea>
BCLR # <data>,<ea>
BKPT # <data>
BRA <label>
BSET Dn,<ea>
BSET # <data>,<ea>
BSR <label>
BTST Dn,<ea>
BTST # <data>,<ea>
CHK <ea>,Dn
CLR <ea>
CMP <ea>,Dn
CMPA <ea>,An
CMPI # <data>,<ea>
CMPM (Ay)+, (Ax)+
DBcc Dn,<label>
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M68000 8-/16-/32-BIT MICROPROCESSOR USER’S MANUAL
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