MC68HC908QL4 Datasheet, PDF (87/226 Pages) Motorola, Inc – Microcontrollers

Registers
8.8 Registers
The IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module. The
INTSCR:
• Shows the state of the IRQ flag
• Clears the IRQ latch
• Masks the IRQ interrupt request
• Controls triggering sensitivity of the IRQ interrupt pin
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
0
0
0
0
IRQF
0
IMASK
ACK
0
0
0
0
0
0
0
= Unimplemented
Figure 8-3. IRQ Status and Control Register (INTSCR)
Bit 0
MODE
0
IRQF — IRQ Flag Bit
This read-only status bit is set when the IRQ interrupt is pending.
1 = IRQ interrupt pending
0 = IRQ interrupt not pending
ACK — IRQ Interrupt Request Acknowledge Bit
Writing a 1 to this write-only bit clears the IRQ latch. ACK always reads 0.
IMASK — IRQ Interrupt Mask Bit
Writing a 1 to this read/write bit disables the IRQ interrupt request.
1 = IRQ interrupt request disabled
0 = IRQ interrupt request enabled
MODE — IRQ Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ pin.
1 = IRQ interrupt request on falling edges and low levels
0 = IRQ interrupt request on falling edges only
MC68HC908QL4 Data Sheet, Rev. 7
Freescale Semiconductor
87