MC68HC908QL4 Datasheet, PDF (195/226 Pages) Motorola, Inc – Microcontrollers

Monitor Module (MON)
V_DD
N.C.
RST (PTA3)
1 μF
1 μF
DB9
2
3
MAX232
1 _C1+
+
3 _C1–
4 _C2+
+
5 _C2–
7
8
V_DD
N.C.
16
15
V+ ²
V– ⁶
+
1 μF
1 μF
+
10 kΩ*
V_DD
1 μF
+
10 kΩ
74HC125
10
6
5
74HC125
9
2
3
4
5
1
OSC1 (PTA5)
IRQ (PTA2)
PTA0
V_DD
0.1 μF
PTA1
N.C.
PTA4
N.C.
V_SS
* Value not critical
Figure 16-12. Monitor Mode Circuit (Internal Clock, No High Voltage)
Table 16-1 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode
may be entered after a power-on reset (POR) and will allow communication at 9600 baud provided one
of the following sets of conditions is met:
• If $FFFE and $FFFF do not contain $FF (programmed state):
– The external clock is 9.8304 MHz
– IRQ = V_TST
• If $FFFE and $FFFF contain $FF (erased state):
– The external clock is 9.8304 MHz
– IRQ = V_DD (this can be implemented through the internal IRQ pullup)
• If $FFFE and $FFFF contain $FF (erased state):
IRQ = V_SS (internal oscillator is selected, no external clock required)
The rising edge of the internal RST signal latches the monitor mode. Once monitor mode is latched, the
values on PTA1 and PTA4 pins can be changed.
Once out of reset, the MCU waits for the host to send eight security bytes (see 16.3.2 Security). After the
security bytes, the MCU sends a break signal (10 consecutive 0s) to the host, indicating that it is ready to
receive a command.
MC68HC908QL4 Data Sheet, Rev. 7
Freescale Semiconductor
195