MC68HC908QL4 Datasheet, PDF (129/226 Pages) Motorola, Inc – Microcontrollers

Low-Power Modes
13.7.1 Wait Mode
In wait mode, the CPU clocks are inactive while the peripheral clocks continue to run. Figure 13-14 shows
the timing for wait mode entry.
ADDRESS BUS WAIT ADDR
WAIT ADDR + 1
SAME
SAME
DATA BUS
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
NOTE: Previous data can be operand data or the WAIT opcode, depending on the last instruction.
Figure 13-14. Wait Mode Entry Timing
A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled.
Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred.
In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the
module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode.
Wait mode can also be exited by a reset (or break in emulation mode). A break interrupt during wait mode
sets the SIM break stop/wait bit, SBSW, in the break status register (BSR). If the COP disable bit, COPD,
in the configuration register is 0, then the computer operating properly module (COP) is enabled and
remains active in wait mode.
Figure 13-15 and Figure 13-16 show the timing for wait recovery.
ADDRESS BUS
$6E0B
$6E0C $00FF $00FE $00FD $00FC
DATA BUS $A6 $A6
$A6
$01
$0B
$6E
EXITSTOPWAIT
NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt
Figure 13-15. Wait Recovery from Interrupt
ADDRESS BUS
$6E0B
32
CYCLES
32
CYCLES
RSTVCTH RSTVCTL
DATA BUS $A6 $A6
$A6
RST⁽¹⁾
BUSCLKX4
1. RST is only available if the RSTEN bit in the CONFIG1 register is set.
Figure 13-16. Wait Recovery from Internal Reset
MC68HC908QL4 Data Sheet, Rev. 7
Freescale Semiconductor
129